Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10080 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T7 |
1 |
| others[1] |
737 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T56 |
1 |
| others[2] |
805 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T66 |
1 |
| others[3] |
1285 |
1 |
|
T1 |
28 |
|
T4 |
6 |
|
T19 |
1 |
| false |
400 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T5 |
1 |
| true |
541 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2349 |
1 |
|
T1 |
22 |
|
T4 |
3 |
|
T5 |
1 |
| others[1] |
2254 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T28 |
1 |
| others[2] |
2376 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T11 |
1 |
| others[3] |
4021 |
1 |
|
T1 |
25 |
|
T3 |
1 |
|
T4 |
4 |
| false |
1252 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T11 |
1 |
| true |
1596 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9516 |
1 |
|
T11 |
3 |
|
T28 |
1 |
|
T19 |
1 |
| others[1] |
274 |
1 |
|
T57 |
1 |
|
T102 |
1 |
|
T40 |
2 |
| others[2] |
290 |
1 |
|
T7 |
1 |
|
T101 |
1 |
|
T55 |
17 |
| others[3] |
470 |
1 |
|
T6 |
1 |
|
T27 |
1 |
|
T50 |
1 |
| false |
161 |
1 |
|
T66 |
1 |
|
T55 |
4 |
|
T117 |
1 |
| true |
3137 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9684 |
1 |
|
T1 |
5 |
|
T11 |
3 |
|
T38 |
94 |
| others[1] |
460 |
1 |
|
T1 |
6 |
|
T4 |
2 |
|
T7 |
1 |
| others[2] |
480 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T16 |
1 |
| others[3] |
827 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T19 |
1 |
| false |
251 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T40 |
1 |
| true |
2146 |
1 |
|
T1 |
43 |
|
T3 |
1 |
|
T4 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9470 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T66 |
1 |
| others[1] |
268 |
1 |
|
T19 |
1 |
|
T18 |
1 |
|
T29 |
1 |
| others[2] |
252 |
1 |
|
T101 |
1 |
|
T55 |
12 |
|
T226 |
1 |
| others[3] |
441 |
1 |
|
T17 |
1 |
|
T104 |
1 |
|
T40 |
2 |
| false |
118 |
1 |
|
T32 |
1 |
|
T55 |
5 |
|
T76 |
8 |
| true |
3299 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9483 |
1 |
|
T11 |
3 |
|
T27 |
1 |
|
T38 |
94 |
| others[1] |
278 |
1 |
|
T69 |
1 |
|
T40 |
1 |
|
T55 |
10 |
| others[2] |
241 |
1 |
|
T21 |
1 |
|
T56 |
1 |
|
T55 |
6 |
| others[3] |
434 |
1 |
|
T66 |
1 |
|
T29 |
1 |
|
T55 |
15 |
| false |
133 |
1 |
|
T102 |
1 |
|
T55 |
3 |
|
T48 |
1 |
| true |
3279 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10007 |
1 |
|
T1 |
9 |
|
T11 |
3 |
|
T27 |
1 |
| others[1] |
820 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T7 |
1 |
| others[2] |
864 |
1 |
|
T1 |
16 |
|
T4 |
6 |
|
T57 |
1 |
| others[3] |
1264 |
1 |
|
T1 |
22 |
|
T4 |
3 |
|
T5 |
1 |
| false |
381 |
1 |
|
T1 |
13 |
|
T4 |
2 |
|
T32 |
1 |
| true |
512 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9993 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T7 |
1 |
| others[1] |
781 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T19 |
1 |
| others[2] |
795 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T40 |
1 |
| others[3] |
1320 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T5 |
1 |
| false |
401 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T57 |
1 |
| true |
526 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2297 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T11 |
1 |
| others[1] |
2407 |
1 |
|
T1 |
17 |
|
T4 |
3 |
|
T5 |
1 |
| others[2] |
2385 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T11 |
1 |
| others[3] |
3959 |
1 |
|
T1 |
26 |
|
T3 |
1 |
|
T4 |
4 |
| false |
1226 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T38 |
7 |
| true |
1542 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9518 |
1 |
|
T16 |
1 |
|
T11 |
3 |
|
T38 |
94 |
| others[1] |
279 |
1 |
|
T17 |
1 |
|
T29 |
1 |
|
T181 |
1 |
| others[2] |
256 |
1 |
|
T66 |
1 |
|
T18 |
1 |
|
T57 |
1 |
| others[3] |
468 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T30 |
1 |
| false |
132 |
1 |
|
T32 |
1 |
|
T55 |
5 |
|
T87 |
1 |
| true |
3163 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9669 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T17 |
1 |
| others[1] |
483 |
1 |
|
T1 |
7 |
|
T3 |
1 |
|
T4 |
2 |
| others[2] |
465 |
1 |
|
T1 |
8 |
|
T5 |
1 |
|
T32 |
1 |
| others[3] |
770 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T16 |
1 |
| false |
253 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T69 |
1 |
| true |
2176 |
1 |
|
T1 |
43 |
|
T4 |
8 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9469 |
1 |
|
T5 |
1 |
|
T11 |
3 |
|
T38 |
94 |
| others[1] |
235 |
1 |
|
T66 |
1 |
|
T55 |
10 |
|
T48 |
1 |
| others[2] |
294 |
1 |
|
T27 |
1 |
|
T21 |
1 |
|
T32 |
1 |
| others[3] |
449 |
1 |
|
T20 |
1 |
|
T56 |
1 |
|
T32 |
1 |
| false |
148 |
1 |
|
T50 |
1 |
|
T57 |
1 |
|
T101 |
1 |
| true |
3221 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9479 |
1 |
|
T5 |
1 |
|
T11 |
3 |
|
T19 |
1 |
| others[1] |
252 |
1 |
|
T40 |
1 |
|
T55 |
7 |
|
T58 |
1 |
| others[2] |
266 |
1 |
|
T69 |
1 |
|
T21 |
1 |
|
T55 |
13 |
| others[3] |
400 |
1 |
|
T32 |
1 |
|
T104 |
1 |
|
T55 |
17 |
| false |
110 |
1 |
|
T40 |
1 |
|
T55 |
3 |
|
T87 |
1 |
| true |
3309 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10033 |
1 |
|
T1 |
12 |
|
T4 |
3 |
|
T7 |
1 |
| others[1] |
765 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T66 |
1 |
| others[2] |
754 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
1372 |
1 |
|
T1 |
23 |
|
T4 |
3 |
|
T19 |
1 |
| false |
395 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T44 |
7 |
| true |
497 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10056 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T5 |
1 |
| others[1] |
794 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T40 |
1 |
| others[2] |
756 |
1 |
|
T1 |
16 |
|
T4 |
4 |
|
T19 |
1 |
| others[3] |
1248 |
1 |
|
T1 |
22 |
|
T4 |
4 |
|
T7 |
1 |
| false |
435 |
1 |
|
T1 |
9 |
|
T69 |
1 |
|
T44 |
6 |
| true |
527 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2420 |
1 |
|
T1 |
18 |
|
T4 |
2 |
|
T38 |
19 |
| others[1] |
2304 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T11 |
1 |
| others[2] |
2329 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T19 |
1 |
| others[3] |
3877 |
1 |
|
T1 |
26 |
|
T4 |
5 |
|
T5 |
1 |
| false |
1300 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T11 |
1 |
| true |
1586 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9522 |
1 |
|
T6 |
1 |
|
T11 |
3 |
|
T38 |
94 |
| others[1] |
252 |
1 |
|
T17 |
1 |
|
T66 |
1 |
|
T56 |
1 |
| others[2] |
272 |
1 |
|
T19 |
1 |
|
T50 |
1 |
|
T18 |
1 |
| others[3] |
437 |
1 |
|
T16 |
1 |
|
T28 |
1 |
|
T40 |
1 |
| false |
136 |
1 |
|
T32 |
2 |
|
T40 |
1 |
|
T55 |
2 |
| true |
3197 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9733 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
435 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T28 |
1 |
| others[2] |
425 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T16 |
1 |
| others[3] |
774 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T56 |
1 |
| false |
235 |
1 |
|
T1 |
4 |
|
T102 |
1 |
|
T40 |
1 |
| true |
2214 |
1 |
|
T1 |
44 |
|
T3 |
1 |
|
T4 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9472 |
1 |
|
T11 |
3 |
|
T19 |
1 |
|
T38 |
94 |
| others[1] |
265 |
1 |
|
T5 |
1 |
|
T57 |
1 |
|
T32 |
1 |
| others[2] |
251 |
1 |
|
T47 |
1 |
|
T40 |
2 |
|
T118 |
1 |
| others[3] |
428 |
1 |
|
T28 |
1 |
|
T29 |
1 |
|
T102 |
1 |
| false |
145 |
1 |
|
T55 |
5 |
|
T226 |
1 |
|
T97 |
1 |
| true |
3255 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9458 |
1 |
|
T5 |
1 |
|
T11 |
3 |
|
T38 |
94 |
| others[1] |
246 |
1 |
|
T19 |
1 |
|
T32 |
1 |
|
T40 |
1 |
| others[2] |
254 |
1 |
|
T50 |
1 |
|
T56 |
1 |
|
T55 |
11 |
| others[3] |
416 |
1 |
|
T40 |
1 |
|
T55 |
8 |
|
T234 |
1 |
| false |
114 |
1 |
|
T40 |
1 |
|
T55 |
8 |
|
T61 |
1 |
| true |
3328 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10000 |
1 |
|
T1 |
11 |
|
T4 |
3 |
|
T11 |
3 |
| others[1] |
761 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T28 |
1 |
| others[2] |
787 |
1 |
|
T1 |
18 |
|
T4 |
3 |
|
T5 |
1 |
| others[3] |
1312 |
1 |
|
T1 |
31 |
|
T4 |
3 |
|
T66 |
1 |
| false |
433 |
1 |
|
T1 |
5 |
|
T4 |
3 |
|
T44 |
4 |
| true |
523 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10026 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T11 |
3 |
| others[1] |
758 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
772 |
1 |
|
T1 |
13 |
|
T4 |
6 |
|
T6 |
1 |
| others[3] |
1297 |
1 |
|
T1 |
26 |
|
T4 |
3 |
|
T19 |
1 |
| false |
429 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T18 |
1 |
| true |
534 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2359 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T7 |
1 |
| others[1] |
2334 |
1 |
|
T1 |
15 |
|
T3 |
1 |
|
T4 |
2 |
| others[2] |
2392 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
3931 |
1 |
|
T1 |
28 |
|
T4 |
7 |
|
T11 |
1 |
| false |
1236 |
1 |
|
T1 |
8 |
|
T5 |
1 |
|
T11 |
1 |
| true |
1564 |
1 |
|
T6 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9482 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T39 |
100 |
| others[1] |
286 |
1 |
|
T6 |
1 |
|
T19 |
1 |
|
T50 |
1 |
| others[2] |
260 |
1 |
|
T5 |
1 |
|
T28 |
1 |
|
T21 |
1 |
| others[3] |
459 |
1 |
|
T7 |
1 |
|
T69 |
1 |
|
T40 |
2 |
| false |
144 |
1 |
|
T40 |
1 |
|
T55 |
6 |
|
T234 |
1 |
| true |
3185 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9667 |
1 |
|
T1 |
4 |
|
T5 |
1 |
|
T11 |
3 |
| others[1] |
464 |
1 |
|
T1 |
8 |
|
T19 |
1 |
|
T12 |
1 |
| others[2] |
452 |
1 |
|
T1 |
6 |
|
T57 |
1 |
|
T30 |
1 |
| others[3] |
779 |
1 |
|
T1 |
19 |
|
T4 |
2 |
|
T50 |
1 |
| false |
242 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T7 |
1 |
| true |
2212 |
1 |
|
T1 |
37 |
|
T3 |
1 |
|
T4 |
10 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9502 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T50 |
1 |
| others[1] |
254 |
1 |
|
T28 |
1 |
|
T104 |
1 |
|
T40 |
1 |
| others[2] |
275 |
1 |
|
T21 |
1 |
|
T181 |
1 |
|
T47 |
1 |
| others[3] |
400 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T19 |
1 |
| false |
156 |
1 |
|
T40 |
1 |
|
T55 |
8 |
|
T113 |
1 |
| true |
3229 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9487 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T39 |
100 |
| others[1] |
262 |
1 |
|
T3 |
1 |
|
T56 |
1 |
|
T55 |
9 |
| others[2] |
252 |
1 |
|
T7 |
1 |
|
T27 |
1 |
|
T55 |
10 |
| others[3] |
447 |
1 |
|
T66 |
1 |
|
T55 |
21 |
|
T113 |
1 |
| false |
138 |
1 |
|
T5 |
1 |
|
T28 |
1 |
|
T55 |
7 |
| true |
3230 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10016 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T11 |
3 |
| others[1] |
757 |
1 |
|
T1 |
12 |
|
T4 |
2 |
|
T57 |
1 |
| others[2] |
810 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T7 |
1 |
| others[3] |
1300 |
1 |
|
T1 |
26 |
|
T4 |
4 |
|
T5 |
1 |
| false |
409 |
1 |
|
T1 |
6 |
|
T4 |
4 |
|
T19 |
1 |
| true |
524 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10019 |
1 |
|
T1 |
14 |
|
T4 |
4 |
|
T5 |
1 |
| others[1] |
784 |
1 |
|
T1 |
11 |
|
T4 |
2 |
|
T7 |
1 |
| others[2] |
807 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T66 |
1 |
| others[3] |
1237 |
1 |
|
T1 |
30 |
|
T4 |
3 |
|
T21 |
1 |
| false |
436 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T17 |
1 |
| true |
533 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2383 |
1 |
|
T1 |
18 |
|
T4 |
6 |
|
T11 |
2 |
| others[1] |
2413 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T19 |
1 |
| others[2] |
2306 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
3963 |
1 |
|
T1 |
26 |
|
T4 |
2 |
|
T7 |
1 |
| false |
1210 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T38 |
10 |
| true |
1541 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9492 |
1 |
|
T17 |
1 |
|
T11 |
3 |
|
T38 |
94 |
| others[1] |
258 |
1 |
|
T57 |
1 |
|
T40 |
1 |
|
T55 |
9 |
| others[2] |
269 |
1 |
|
T7 |
1 |
|
T28 |
1 |
|
T181 |
1 |
| others[3] |
465 |
1 |
|
T27 |
1 |
|
T19 |
1 |
|
T21 |
1 |
| false |
154 |
1 |
|
T40 |
1 |
|
T55 |
7 |
|
T123 |
1 |
| true |
3178 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |