Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9662 |
1 |
|
T1 |
7 |
|
T4 |
2 |
|
T11 |
3 |
| others[1] |
462 |
1 |
|
T1 |
7 |
|
T3 |
1 |
|
T4 |
1 |
| others[2] |
475 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
782 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T6 |
1 |
| false |
231 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T17 |
1 |
| true |
2204 |
1 |
|
T1 |
35 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9495 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T39 |
100 |
| others[1] |
262 |
1 |
|
T28 |
1 |
|
T104 |
1 |
|
T207 |
1 |
| others[2] |
257 |
1 |
|
T19 |
1 |
|
T40 |
1 |
|
T55 |
7 |
| others[3] |
458 |
1 |
|
T50 |
1 |
|
T69 |
1 |
|
T57 |
1 |
| false |
137 |
1 |
|
T32 |
1 |
|
T101 |
1 |
|
T40 |
1 |
| true |
3207 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9492 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T39 |
100 |
| others[1] |
256 |
1 |
|
T29 |
1 |
|
T32 |
1 |
|
T55 |
15 |
| others[2] |
257 |
1 |
|
T102 |
1 |
|
T55 |
13 |
|
T48 |
1 |
| others[3] |
447 |
1 |
|
T5 |
1 |
|
T57 |
1 |
|
T40 |
2 |
| false |
151 |
1 |
|
T7 |
1 |
|
T50 |
1 |
|
T69 |
1 |
| true |
3213 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10005 |
1 |
|
T1 |
22 |
|
T4 |
1 |
|
T11 |
3 |
| others[1] |
815 |
1 |
|
T1 |
10 |
|
T4 |
4 |
|
T5 |
1 |
| others[2] |
802 |
1 |
|
T1 |
15 |
|
T4 |
2 |
|
T19 |
1 |
| others[3] |
1294 |
1 |
|
T1 |
26 |
|
T4 |
5 |
|
T7 |
1 |
| false |
389 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T44 |
6 |
| true |
511 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10029 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T7 |
1 |
| others[1] |
793 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T50 |
1 |
| others[2] |
763 |
1 |
|
T1 |
25 |
|
T4 |
4 |
|
T102 |
1 |
| others[3] |
1291 |
1 |
|
T1 |
22 |
|
T4 |
3 |
|
T5 |
1 |
| false |
417 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T6 |
1 |
| true |
523 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2350 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T7 |
1 |
| others[1] |
2413 |
1 |
|
T1 |
15 |
|
T4 |
3 |
|
T11 |
1 |
| others[2] |
2372 |
1 |
|
T1 |
16 |
|
T5 |
1 |
|
T11 |
1 |
| others[3] |
3898 |
1 |
|
T1 |
29 |
|
T4 |
3 |
|
T11 |
1 |
| false |
1253 |
1 |
|
T1 |
8 |
|
T4 |
4 |
|
T38 |
13 |
| true |
1530 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9495 |
1 |
|
T16 |
1 |
|
T11 |
3 |
|
T38 |
94 |
| others[1] |
263 |
1 |
|
T181 |
1 |
|
T55 |
11 |
|
T226 |
1 |
| others[2] |
284 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T17 |
1 |
| others[3] |
434 |
1 |
|
T21 |
1 |
|
T32 |
1 |
|
T104 |
1 |
| false |
155 |
1 |
|
T19 |
1 |
|
T50 |
1 |
|
T32 |
1 |
| true |
3185 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9685 |
1 |
|
T1 |
3 |
|
T4 |
4 |
|
T11 |
3 |
| others[1] |
488 |
1 |
|
T1 |
9 |
|
T5 |
1 |
|
T29 |
1 |
| others[2] |
434 |
1 |
|
T1 |
8 |
|
T4 |
2 |
|
T69 |
1 |
| others[3] |
826 |
1 |
|
T1 |
9 |
|
T4 |
2 |
|
T12 |
1 |
| false |
233 |
1 |
|
T1 |
4 |
|
T16 |
1 |
|
T7 |
1 |
| true |
2150 |
1 |
|
T1 |
45 |
|
T3 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9501 |
1 |
|
T11 |
3 |
|
T27 |
1 |
|
T38 |
94 |
| others[1] |
268 |
1 |
|
T181 |
1 |
|
T32 |
1 |
|
T55 |
12 |
| others[2] |
243 |
1 |
|
T40 |
1 |
|
T207 |
1 |
|
T55 |
10 |
| others[3] |
421 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T40 |
1 |
| false |
128 |
1 |
|
T32 |
1 |
|
T55 |
2 |
|
T87 |
2 |
| true |
3255 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9481 |
1 |
|
T11 |
3 |
|
T28 |
1 |
|
T38 |
94 |
| others[1] |
243 |
1 |
|
T32 |
1 |
|
T55 |
7 |
|
T48 |
2 |
| others[2] |
249 |
1 |
|
T5 |
1 |
|
T29 |
1 |
|
T55 |
8 |
| others[3] |
433 |
1 |
|
T7 |
1 |
|
T50 |
1 |
|
T66 |
1 |
| false |
134 |
1 |
|
T55 |
7 |
|
T22 |
1 |
|
T76 |
7 |
| true |
3276 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10005 |
1 |
|
T1 |
16 |
|
T4 |
2 |
|
T5 |
1 |
| others[1] |
761 |
1 |
|
T1 |
22 |
|
T4 |
2 |
|
T28 |
1 |
| others[2] |
796 |
1 |
|
T1 |
10 |
|
T4 |
3 |
|
T66 |
1 |
| others[3] |
1332 |
1 |
|
T1 |
25 |
|
T4 |
4 |
|
T19 |
1 |
| false |
405 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T102 |
1 |
| true |
517 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10069 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T11 |
3 |
| others[1] |
770 |
1 |
|
T1 |
13 |
|
T4 |
4 |
|
T66 |
1 |
| others[2] |
744 |
1 |
|
T1 |
15 |
|
T50 |
1 |
|
T57 |
1 |
| others[3] |
1295 |
1 |
|
T1 |
25 |
|
T4 |
7 |
|
T5 |
1 |
| false |
389 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T7 |
1 |
| true |
549 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2389 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T5 |
1 |
| others[1] |
2344 |
1 |
|
T1 |
14 |
|
T4 |
4 |
|
T11 |
1 |
| others[2] |
2378 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T38 |
17 |
| others[3] |
3903 |
1 |
|
T1 |
26 |
|
T4 |
3 |
|
T11 |
1 |
| false |
1234 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T7 |
1 |
| true |
1568 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9499 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T11 |
3 |
| others[1] |
270 |
1 |
|
T5 |
1 |
|
T66 |
1 |
|
T29 |
1 |
| others[2] |
306 |
1 |
|
T28 |
1 |
|
T55 |
10 |
|
T93 |
1 |
| others[3] |
435 |
1 |
|
T27 |
1 |
|
T50 |
1 |
|
T69 |
1 |
| false |
143 |
1 |
|
T6 |
1 |
|
T20 |
1 |
|
T40 |
1 |
| true |
3163 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9660 |
1 |
|
T1 |
10 |
|
T4 |
2 |
|
T6 |
1 |
| others[1] |
461 |
1 |
|
T1 |
6 |
|
T4 |
2 |
|
T27 |
1 |
| others[2] |
459 |
1 |
|
T1 |
10 |
|
T50 |
1 |
|
T12 |
1 |
| others[3] |
748 |
1 |
|
T1 |
8 |
|
T3 |
1 |
|
T4 |
3 |
| false |
216 |
1 |
|
T1 |
2 |
|
T40 |
1 |
|
T44 |
1 |
| true |
2272 |
1 |
|
T1 |
42 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9478 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T39 |
100 |
| others[1] |
260 |
1 |
|
T7 |
1 |
|
T50 |
1 |
|
T207 |
1 |
| others[2] |
284 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T181 |
1 |
| others[3] |
431 |
1 |
|
T29 |
1 |
|
T21 |
1 |
|
T104 |
1 |
| false |
157 |
1 |
|
T40 |
1 |
|
T55 |
9 |
|
T203 |
1 |
| true |
3206 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9468 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T39 |
100 |
| others[1] |
247 |
1 |
|
T32 |
1 |
|
T55 |
8 |
|
T87 |
2 |
| others[2] |
257 |
1 |
|
T50 |
1 |
|
T66 |
1 |
|
T40 |
1 |
| others[3] |
429 |
1 |
|
T7 |
1 |
|
T47 |
1 |
|
T40 |
1 |
| false |
146 |
1 |
|
T55 |
4 |
|
T123 |
1 |
|
T76 |
7 |
| true |
3269 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10021 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T5 |
1 |
| others[1] |
720 |
1 |
|
T1 |
16 |
|
T4 |
3 |
|
T44 |
4 |
| others[2] |
844 |
1 |
|
T1 |
17 |
|
T4 |
3 |
|
T66 |
1 |
| others[3] |
1282 |
1 |
|
T1 |
26 |
|
T4 |
2 |
|
T7 |
1 |
| false |
423 |
1 |
|
T1 |
5 |
|
T4 |
3 |
|
T44 |
1 |
| true |
526 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10014 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T11 |
3 |
| others[1] |
795 |
1 |
|
T1 |
14 |
|
T4 |
2 |
|
T17 |
1 |
| others[2] |
776 |
1 |
|
T1 |
16 |
|
T4 |
5 |
|
T21 |
1 |
| others[3] |
1259 |
1 |
|
T1 |
26 |
|
T4 |
4 |
|
T7 |
1 |
| false |
456 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T5 |
1 |
| true |
516 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2382 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
2288 |
1 |
|
T1 |
19 |
|
T4 |
4 |
|
T38 |
13 |
| others[2] |
2437 |
1 |
|
T1 |
18 |
|
T4 |
4 |
|
T11 |
1 |
| others[3] |
3944 |
1 |
|
T1 |
17 |
|
T4 |
3 |
|
T38 |
28 |
| false |
1242 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T11 |
2 |
| true |
1523 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9473 |
1 |
|
T11 |
3 |
|
T38 |
94 |
|
T39 |
100 |
| others[1] |
293 |
1 |
|
T6 |
1 |
|
T40 |
2 |
|
T55 |
13 |
| others[2] |
283 |
1 |
|
T16 |
1 |
|
T27 |
1 |
|
T102 |
1 |
| others[3] |
458 |
1 |
|
T7 |
1 |
|
T19 |
1 |
|
T18 |
1 |
| false |
133 |
1 |
|
T3 |
1 |
|
T181 |
1 |
|
T104 |
1 |
| true |
3176 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9713 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T7 |
1 |
| others[1] |
473 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T16 |
1 |
| others[2] |
462 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T21 |
1 |
| others[3] |
749 |
1 |
|
T1 |
16 |
|
T3 |
1 |
|
T4 |
5 |
| false |
253 |
1 |
|
T1 |
2 |
|
T5 |
1 |
|
T47 |
1 |
| true |
2166 |
1 |
|
T1 |
44 |
|
T4 |
5 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9480 |
1 |
|
T17 |
1 |
|
T11 |
3 |
|
T38 |
94 |
| others[1] |
272 |
1 |
|
T66 |
1 |
|
T69 |
1 |
|
T32 |
1 |
| others[2] |
253 |
1 |
|
T19 |
1 |
|
T18 |
1 |
|
T57 |
1 |
| others[3] |
454 |
1 |
|
T7 |
1 |
|
T27 |
1 |
|
T181 |
1 |
| false |
139 |
1 |
|
T56 |
1 |
|
T55 |
3 |
|
T123 |
1 |
| true |
3218 |
1 |
|
T1 |
78 |
|
T3 |
1 |
|
T4 |
13 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9456 |
1 |
|
T11 |
3 |
|
T27 |
1 |
|
T28 |
1 |
| others[1] |
251 |
1 |
|
T3 |
1 |
|
T66 |
1 |
|
T56 |
1 |
| others[2] |
249 |
1 |
|
T19 |
1 |
|
T40 |
1 |
|
T55 |
9 |
| others[3] |
423 |
1 |
|
T50 |
1 |
|
T29 |
1 |
|
T104 |
1 |
| false |
143 |
1 |
|
T102 |
1 |
|
T40 |
1 |
|
T55 |
3 |
| true |
3294 |
1 |
|
T1 |
78 |
|
T4 |
13 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9995 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T11 |
3 |
| others[1] |
755 |
1 |
|
T1 |
13 |
|
T4 |
3 |
|
T66 |
1 |
| others[2] |
800 |
1 |
|
T1 |
21 |
|
T4 |
4 |
|
T5 |
1 |
| others[3] |
1350 |
1 |
|
T1 |
28 |
|
T4 |
3 |
|
T7 |
1 |
| false |
412 |
1 |
|
T1 |
5 |
|
T4 |
2 |
|
T56 |
1 |
| true |
504 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |