Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	223216	1		T1	37		T4	9		T5	506
auto[FlashEraseBank]	254573	1		T1	41		T3	20		T4	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	262915	1		T3	20		T4	3		T5	975
auto[FlashOpProgram]	195507	1		T1	78		T4	4		T6	1
auto[FlashOpErase]	15367	1		T4	6		T11	10		T38	137
auto[FlashOpInvalid]	4000	1		T39	200		T95	200		T243	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	262915	1		T3	20		T4	3		T5	975
op[FlashOpProgram]	195507	1		T1	78		T4	4		T6	1
op[FlashOpErase]	15367	1		T4	6		T11	10		T38	137
read_erase_read	731	1		T25	2		T101	28		T54	1
read_prog_read	1295	1		T16	2		T27	9		T28	8

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	337184	1		T1	78		T4	13		T5	939
auto[FlashPartInfo]	136311	1		T6	11		T16	8		T17	109
auto[FlashPartInfo1]	939	1		T17	23		T27	6		T28	2
auto[FlashPartInfo2]	3355	1		T3	20		T5	36		T16	3

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	198322	1		T4	3		T5	939		T16	3
auto[FlashPartData]	auto[FlashOpProgram]	131216	1		T1	78		T4	4		T6	1
auto[FlashPartData]	auto[FlashOpErase]	3726	1		T4	6		T11	4		T39	97
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T39	194		T95	192		T243	196
auto[FlashPartInfo]	auto[FlashOpRead]	61722	1		T6	11		T16	7		T17	109
auto[FlashPartInfo]	auto[FlashOpProgram]	62953	1		T16	1		T11	192		T27	268
auto[FlashPartInfo]	auto[FlashOpErase]	11578	1		T11	6		T38	137		T24	12
auto[FlashPartInfo]	auto[FlashOpInvalid]	58	1		T39	4		T95	8		T243	4
auto[FlashPartInfo1]	auto[FlashOpRead]	768	1		T17	23		T27	6		T28	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T78	1		T79	1		T80	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T78	1		T79	1		T83	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T78	2		T79	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2103	1		T3	20		T5	36		T16	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	1174	1		T27	3		T28	13		T39	1
auto[FlashPartInfo2]	auto[FlashOpErase]	60	1		T39	1		T40	1		T93	11
auto[FlashPartInfo2]	auto[FlashOpInvalid]	18	1		T39	2		T78	2		T120	2