Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29675	1		T4	13		T11	8		T38	292
auto[1]	77	1		T30	1		T97	2		T390	7
auto[2]	199	1		T30	1		T277	4		T98	41
auto[3]	406	1		T6	1		T181	1		T101	68

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7618	1		T4	3		T6	1		T11	2
evic_idx[1]	7604	1		T4	3		T11	2		T38	73
evic_idx[2]	7568	1		T4	3		T11	2		T38	73
evic_idx[3]	7567	1		T4	4		T11	2		T38	73

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29219	1		T11	4		T38	292		T39	400
evic_op[2]	454	1		T4	1		T6	1		T181	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7186	1		T11	1		T38	73		T39	100
evic_idx[0]	evic_op[1]	auto[1]	20	1		T390	2		T391	1		T392	17
evic_idx[0]	evic_op[1]	auto[2]	17	1		T393	17		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	107	1		T101	19		T207	20		T394	14
evic_idx[0]	evic_op[2]	auto[0]	67	1		T227	4		T64	1		T228	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T97	1		T183	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	39	1		T277	2		T98	13		T99	3
evic_idx[0]	evic_op[2]	auto[3]	9	1		T6	1		T209	1		T288	1
evic_idx[1]	evic_op[1]	auto[0]	7190	1		T11	1		T38	73		T39	100
evic_idx[1]	evic_op[1]	auto[1]	18	1		T391	2		T392	16		-	-
evic_idx[1]	evic_op[1]	auto[2]	13	1		T393	13		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	105	1		T101	21		T207	22		T394	11
evic_idx[1]	evic_op[2]	auto[0]	63	1		T227	4		T228	4		T395	4
evic_idx[1]	evic_op[2]	auto[1]	4	1		T30	1		T183	1		T396	1
evic_idx[1]	evic_op[2]	auto[2]	34	1		T277	2		T98	9		T99	4
evic_idx[1]	evic_op[2]	auto[3]	6	1		T397	1		T398	1		T399	1
evic_idx[2]	evic_op[1]	auto[0]	7189	1		T11	1		T38	73		T39	100
evic_idx[2]	evic_op[1]	auto[1]	13	1		T390	4		T391	2		T392	7
evic_idx[2]	evic_op[1]	auto[2]	8	1		T393	8		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	77	1		T101	15		T207	16		T394	5
evic_idx[2]	evic_op[2]	auto[0]	66	1		T227	4		T228	4		T395	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T400	1		T396	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	30	1		T98	6		T99	5		T401	9
evic_idx[2]	evic_op[2]	auto[3]	12	1		T181	1		T402	1		T290	1
evic_idx[3]	evic_op[1]	auto[0]	7181	1		T11	1		T38	73		T39	100
evic_idx[3]	evic_op[1]	auto[1]	16	1		T390	1		T391	6		T392	9
evic_idx[3]	evic_op[1]	auto[2]	6	1		T393	6		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	73	1		T101	13		T207	10		T394	13
evic_idx[3]	evic_op[2]	auto[0]	65	1		T4	1		T227	4		T228	4
evic_idx[3]	evic_op[2]	auto[1]	2	1		T97	1		T396	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	36	1		T30	1		T98	13		T99	4
evic_idx[3]	evic_op[2]	auto[3]	17	1		T31	1		T96	1		T280	1