Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
4966 | 
1 | 
 | 
T44 | 
80 | 
 | 
T45 | 
89 | 
 | 
T46 | 
115 | 
| instr_types[0] | 
5985 | 
1 | 
 | 
T44 | 
214 | 
 | 
T45 | 
179 | 
 | 
T46 | 
303 | 
| instr_types[1] | 
4609000 | 
1 | 
 | 
T4 | 
157 | 
 | 
T5 | 
16465 | 
 | 
T6 | 
9 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4618227 | 
1 | 
 | 
T4 | 
157 | 
 | 
T5 | 
16465 | 
 | 
T6 | 
9 | 
| auto[1] | 
1724 | 
1 | 
 | 
T44 | 
134 | 
 | 
T45 | 
136 | 
 | 
T46 | 
176 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
4646 | 
1 | 
 | 
T44 | 
55 | 
 | 
T45 | 
63 | 
 | 
T46 | 
76 | 
| auto[0] | 
instr_types[0] | 
5279 | 
1 | 
 | 
T44 | 
140 | 
 | 
T45 | 
130 | 
 | 
T46 | 
257 | 
| auto[0] | 
instr_types[1] | 
4608302 | 
1 | 
 | 
T4 | 
157 | 
 | 
T5 | 
16465 | 
 | 
T6 | 
9 | 
| auto[1] | 
others | 
320 | 
1 | 
 | 
T44 | 
25 | 
 | 
T45 | 
26 | 
 | 
T46 | 
39 | 
| auto[1] | 
instr_types[0] | 
706 | 
1 | 
 | 
T44 | 
74 | 
 | 
T45 | 
49 | 
 | 
T46 | 
46 | 
| auto[1] | 
instr_types[1] | 
698 | 
1 | 
 | 
T44 | 
35 | 
 | 
T45 | 
61 | 
 | 
T46 | 
91 |