Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	20625	1		T69	7797		T279	1377		T334	8666
rd_lvl[2]	32339	1		T17	1495		T69	3925		T115	1662
rd_lvl[3]	30135	1		T17	1190		T115	1625		T279	526
rd_lvl[4]	29289	1		T5	2759		T17	244		T115	358
rd_lvl[5]	18821	1		T5	1141		T17	1012		T115	1247
rd_lvl[6]	14982	1		T17	1212		T69	1		T115	1419
rd_lvl[7]	8484	1		T17	15		T115	127		T289	1184
rd_lvl[8]	17642	1		T17	15		T115	126		T289	791
rd_lvl[9]	7757	1		T17	14		T115	125		T289	72
rd_lvl[10]	4877	1		T289	67		T279	79		T208	1
rd_lvl[11]	5380	1		T26	736		T279	1401		T285	52
rd_lvl[12]	3530	1		T17	27		T115	4		T26	397
rd_lvl[13]	3465	1		T17	27		T18	475		T115	2
rd_lvl[14]	7714	1		T18	526		T26	50		T335	424
rd_lvl[15]	7770	1		T19	456		T335	285		T278	699