Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	315375	1		T1	2		T2	1		T3	2
all_pins[1]	315375	1		T1	2		T2	1		T3	2
all_pins[2]	315375	1		T1	2		T2	1		T3	2
all_pins[3]	315375	1		T1	2		T2	1		T3	2
all_pins[4]	315375	1		T1	2		T2	1		T3	2
all_pins[5]	315375	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1567676	1		T1	12		T2	6		T3	12
values[0x1]	324574	1		T5	4875		T17	6144		T19	1616
transitions[0x0=>0x1]	290918	1		T5	3900		T17	5388		T19	1264
transitions[0x1=>0x0]	290907	1		T5	3900		T17	5388		T19	1264

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	315230	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	145	1		T264	5		T327	1		T328	7
all_pins[0]	transitions[0x0=>0x1]	76	1		T264	2		T328	1		T330	3
all_pins[0]	transitions[0x1=>0x0]	78	1		T264	1		T327	4		T329	3
all_pins[1]	values[0x0]	315228	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	147	1		T264	4		T327	5		T328	6
all_pins[1]	transitions[0x0=>0x1]	121	1		T264	3		T327	5		T328	4
all_pins[1]	transitions[0x1=>0x0]	3170	1		T19	176		T278	383		T338	1
all_pins[2]	values[0x0]	312179	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	3196	1		T19	176		T278	383		T338	1
all_pins[2]	transitions[0x0=>0x1]	45	1		T264	2		T328	2		T330	1
all_pins[2]	transitions[0x1=>0x0]	212977	1		T5	3900		T17	5251		T19	456
all_pins[3]	values[0x0]	99247	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	216128	1		T5	3900		T17	5251		T19	632
all_pins[3]	transitions[0x0=>0x1]	185765	1		T5	2925		T17	4495		T19	456
all_pins[3]	transitions[0x1=>0x0]	74547	1		T17	137		T19	632		T18	1032
all_pins[4]	values[0x0]	210465	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	104910	1		T5	975		T17	893		T19	808
all_pins[4]	transitions[0x0=>0x1]	104900	1		T5	975		T17	893		T19	808
all_pins[4]	transitions[0x1=>0x0]	38	1		T264	3		T328	3		T330	1
all_pins[5]	values[0x0]	315327	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	48	1		T264	3		T328	3		T330	1
all_pins[5]	transitions[0x0=>0x1]	11	1		T264	1		T339	1		T340	2
all_pins[5]	transitions[0x1=>0x0]	97	1		T264	2		T327	1		T328	3