| T319 |
/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.1039336145 |
|
|
Mar 07 03:14:58 PM PST 24 |
Mar 07 03:18:05 PM PST 24 |
2302949300 ps |
| T1076 |
/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2787719312 |
|
|
Mar 07 03:06:38 PM PST 24 |
Mar 07 03:07:00 PM PST 24 |
89701600 ps |
| T1077 |
/workspace/coverage/default/12.flash_ctrl_phy_arb.2202819091 |
|
|
Mar 07 03:12:43 PM PST 24 |
Mar 07 03:18:43 PM PST 24 |
2707989800 ps |
| T1078 |
/workspace/coverage/default/29.flash_ctrl_otp_reset.3526365729 |
|
|
Mar 07 03:17:02 PM PST 24 |
Mar 07 03:19:13 PM PST 24 |
73302900 ps |
| T1079 |
/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.258982462 |
|
|
Mar 07 03:13:34 PM PST 24 |
Mar 07 03:16:52 PM PST 24 |
9018196200 ps |
| T1080 |
/workspace/coverage/default/27.flash_ctrl_alert_test.4152065487 |
|
|
Mar 07 03:16:53 PM PST 24 |
Mar 07 03:17:08 PM PST 24 |
102126900 ps |
| T1081 |
/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.4240290730 |
|
|
Mar 07 03:05:37 PM PST 24 |
Mar 07 03:06:08 PM PST 24 |
37199000 ps |
| T1082 |
/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.2763223592 |
|
|
Mar 07 03:14:57 PM PST 24 |
Mar 07 03:15:10 PM PST 24 |
72129800 ps |
| T1083 |
/workspace/coverage/default/20.flash_ctrl_alert_test.2248775911 |
|
|
Mar 07 03:15:52 PM PST 24 |
Mar 07 03:16:06 PM PST 24 |
78826600 ps |
| T1084 |
/workspace/coverage/default/2.flash_ctrl_disable.587512489 |
|
|
Mar 07 03:05:45 PM PST 24 |
Mar 07 03:06:07 PM PST 24 |
12967500 ps |
| T1085 |
/workspace/coverage/default/9.flash_ctrl_phy_arb.2851934003 |
|
|
Mar 07 03:11:17 PM PST 24 |
Mar 07 03:17:52 PM PST 24 |
79537500 ps |
| T1086 |
/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.1394821952 |
|
|
Mar 07 03:13:43 PM PST 24 |
Mar 07 03:13:56 PM PST 24 |
15499900 ps |
| T1087 |
/workspace/coverage/default/1.flash_ctrl_fs_sup.3333055305 |
|
|
Mar 07 03:04:44 PM PST 24 |
Mar 07 03:05:25 PM PST 24 |
1296521600 ps |
| T1088 |
/workspace/coverage/default/1.flash_ctrl_erase_suspend.1902299958 |
|
|
Mar 07 03:03:32 PM PST 24 |
Mar 07 03:09:24 PM PST 24 |
5802512700 ps |
| T1089 |
/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1999024213 |
|
|
Mar 07 03:15:40 PM PST 24 |
Mar 07 03:15:54 PM PST 24 |
48715500 ps |
| T1090 |
/workspace/coverage/default/14.flash_ctrl_rand_ops.2672026052 |
|
|
Mar 07 03:13:25 PM PST 24 |
Mar 07 03:16:50 PM PST 24 |
146243400 ps |
| T1091 |
/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3479428899 |
|
|
Mar 07 03:15:15 PM PST 24 |
Mar 07 03:18:56 PM PST 24 |
23677166600 ps |
| T1092 |
/workspace/coverage/default/47.flash_ctrl_connect.173244126 |
|
|
Mar 07 03:19:06 PM PST 24 |
Mar 07 03:19:22 PM PST 24 |
24618900 ps |
| T1093 |
/workspace/coverage/default/0.flash_ctrl_host_dir_rd.1734804324 |
|
|
Mar 07 03:01:37 PM PST 24 |
Mar 07 03:02:14 PM PST 24 |
75033500 ps |
| T1094 |
/workspace/coverage/default/2.flash_ctrl_prog_reset.2362538558 |
|
|
Mar 07 03:05:41 PM PST 24 |
Mar 07 03:05:56 PM PST 24 |
38030200 ps |
| T1095 |
/workspace/coverage/default/40.flash_ctrl_connect.516053937 |
|
|
Mar 07 03:18:32 PM PST 24 |
Mar 07 03:18:48 PM PST 24 |
16535500 ps |
| T1096 |
/workspace/coverage/default/3.flash_ctrl_erase_suspend.2249173623 |
|
|
Mar 07 03:06:29 PM PST 24 |
Mar 07 03:12:38 PM PST 24 |
2847771600 ps |
| T1097 |
/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.976250789 |
|
|
Mar 07 03:03:14 PM PST 24 |
Mar 07 03:03:28 PM PST 24 |
73191600 ps |
| T1098 |
/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1209041419 |
|
|
Mar 07 03:15:22 PM PST 24 |
Mar 07 03:16:11 PM PST 24 |
929443900 ps |
| T1099 |
/workspace/coverage/default/40.flash_ctrl_sec_info_access.4247836744 |
|
|
Mar 07 03:18:36 PM PST 24 |
Mar 07 03:19:50 PM PST 24 |
3203400100 ps |
| T1100 |
/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.270952777 |
|
|
Mar 07 03:15:40 PM PST 24 |
Mar 07 03:17:26 PM PST 24 |
15485458000 ps |
| T1101 |
/workspace/coverage/default/17.flash_ctrl_mp_regions.3516790577 |
|
|
Mar 07 03:14:40 PM PST 24 |
Mar 07 03:17:29 PM PST 24 |
9399600600 ps |
| T1102 |
/workspace/coverage/default/14.flash_ctrl_sec_info_access.1781392396 |
|
|
Mar 07 03:13:43 PM PST 24 |
Mar 07 03:14:51 PM PST 24 |
3297007700 ps |
| T1103 |
/workspace/coverage/default/0.flash_ctrl_oversize_error.1697556313 |
|
|
Mar 07 03:02:32 PM PST 24 |
Mar 07 03:05:14 PM PST 24 |
3373883500 ps |
| T1104 |
/workspace/coverage/default/29.flash_ctrl_alert_test.4040461725 |
|
|
Mar 07 03:17:12 PM PST 24 |
Mar 07 03:17:26 PM PST 24 |
116870100 ps |
| T1105 |
/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2185053054 |
|
|
Mar 07 03:05:59 PM PST 24 |
Mar 07 03:06:36 PM PST 24 |
850356400 ps |
| T1106 |
/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2625282680 |
|
|
Mar 07 03:17:48 PM PST 24 |
Mar 07 03:18:19 PM PST 24 |
27195300 ps |
| T388 |
/workspace/coverage/default/12.flash_ctrl_sec_info_access.3348788367 |
|
|
Mar 07 03:12:53 PM PST 24 |
Mar 07 03:13:57 PM PST 24 |
2132217600 ps |
| T1107 |
/workspace/coverage/default/3.flash_ctrl_oversize_error.1632549448 |
|
|
Mar 07 03:06:49 PM PST 24 |
Mar 07 03:09:42 PM PST 24 |
952423000 ps |
| T1108 |
/workspace/coverage/default/16.flash_ctrl_rw.3366601866 |
|
|
Mar 07 03:14:31 PM PST 24 |
Mar 07 03:24:28 PM PST 24 |
27609849900 ps |
| T1109 |
/workspace/coverage/default/12.flash_ctrl_alert_test.2010225130 |
|
|
Mar 07 03:13:09 PM PST 24 |
Mar 07 03:13:22 PM PST 24 |
27726100 ps |
| T1110 |
/workspace/coverage/default/3.flash_ctrl_fs_sup.2086647065 |
|
|
Mar 07 03:07:09 PM PST 24 |
Mar 07 03:07:44 PM PST 24 |
534720600 ps |
| T1111 |
/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.4176194288 |
|
|
Mar 07 03:03:33 PM PST 24 |
Mar 07 03:05:34 PM PST 24 |
731250600 ps |
| T1112 |
/workspace/coverage/default/0.flash_ctrl_fetch_code.462715573 |
|
|
Mar 07 03:02:00 PM PST 24 |
Mar 07 03:02:27 PM PST 24 |
1041446200 ps |
| T1113 |
/workspace/coverage/default/15.flash_ctrl_otp_reset.3499500038 |
|
|
Mar 07 03:13:58 PM PST 24 |
Mar 07 03:16:13 PM PST 24 |
41413300 ps |
| T1114 |
/workspace/coverage/default/37.flash_ctrl_disable.1172756418 |
|
|
Mar 07 03:18:12 PM PST 24 |
Mar 07 03:18:34 PM PST 24 |
16679400 ps |
| T1115 |
/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2948215580 |
|
|
Mar 07 03:15:16 PM PST 24 |
Mar 07 03:15:48 PM PST 24 |
68531300 ps |
| T1116 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.486615119 |
|
|
Mar 07 03:04:16 PM PST 24 |
Mar 07 03:04:47 PM PST 24 |
50156900 ps |
| T1117 |
/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2094385753 |
|
|
Mar 07 03:12:55 PM PST 24 |
Mar 07 03:13:26 PM PST 24 |
31905000 ps |
| T1118 |
/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.379133762 |
|
|
Mar 07 03:14:39 PM PST 24 |
Mar 07 03:18:06 PM PST 24 |
30798779500 ps |
| T1119 |
/workspace/coverage/default/7.flash_ctrl_smoke.171104424 |
|
|
Mar 07 03:09:56 PM PST 24 |
Mar 07 03:10:48 PM PST 24 |
81203100 ps |
| T1120 |
/workspace/coverage/default/0.flash_ctrl_sw_op.3672855265 |
|
|
Mar 07 03:01:36 PM PST 24 |
Mar 07 03:02:03 PM PST 24 |
133204100 ps |
| T1121 |
/workspace/coverage/default/15.flash_ctrl_rw_evict.3263441895 |
|
|
Mar 07 03:14:08 PM PST 24 |
Mar 07 03:14:40 PM PST 24 |
42007100 ps |
| T1122 |
/workspace/coverage/default/2.flash_ctrl_rw_evict.3407045119 |
|
|
Mar 07 03:05:37 PM PST 24 |
Mar 07 03:06:09 PM PST 24 |
51662500 ps |
| T1123 |
/workspace/coverage/default/69.flash_ctrl_otp_reset.851067037 |
|
|
Mar 07 03:19:27 PM PST 24 |
Mar 07 03:21:43 PM PST 24 |
151845500 ps |
| T1124 |
/workspace/coverage/default/5.flash_ctrl_invalid_op.655080645 |
|
|
Mar 07 03:08:34 PM PST 24 |
Mar 07 03:10:04 PM PST 24 |
4007895300 ps |
| T374 |
/workspace/coverage/default/2.flash_ctrl_sec_info_access.1165876172 |
|
|
Mar 07 03:05:45 PM PST 24 |
Mar 07 03:06:51 PM PST 24 |
6650898700 ps |
| T1125 |
/workspace/coverage/default/3.flash_ctrl_rw.1548312268 |
|
|
Mar 07 03:06:39 PM PST 24 |
Mar 07 03:16:52 PM PST 24 |
3628928800 ps |
| T1126 |
/workspace/coverage/default/6.flash_ctrl_rw_serr.175030163 |
|
|
Mar 07 03:09:16 PM PST 24 |
Mar 07 03:20:58 PM PST 24 |
22508891800 ps |
| T1127 |
/workspace/coverage/default/19.flash_ctrl_rw.3840271876 |
|
|
Mar 07 03:15:22 PM PST 24 |
Mar 07 03:24:15 PM PST 24 |
3181331500 ps |
| T1128 |
/workspace/coverage/default/18.flash_ctrl_alert_test.105371941 |
|
|
Mar 07 03:15:22 PM PST 24 |
Mar 07 03:15:36 PM PST 24 |
65811600 ps |
| T1129 |
/workspace/coverage/default/39.flash_ctrl_alert_test.1213565046 |
|
|
Mar 07 03:18:33 PM PST 24 |
Mar 07 03:18:47 PM PST 24 |
236020700 ps |
| T1130 |
/workspace/coverage/default/6.flash_ctrl_rw_derr.3192742284 |
|
|
Mar 07 03:09:29 PM PST 24 |
Mar 07 03:19:51 PM PST 24 |
3592530800 ps |
| T1131 |
/workspace/coverage/default/10.flash_ctrl_alert_test.3441868250 |
|
|
Mar 07 03:12:09 PM PST 24 |
Mar 07 03:12:24 PM PST 24 |
45191500 ps |
| T1132 |
/workspace/coverage/default/30.flash_ctrl_sec_info_access.1427461832 |
|
|
Mar 07 03:17:27 PM PST 24 |
Mar 07 03:18:42 PM PST 24 |
923705000 ps |
| T1133 |
/workspace/coverage/default/0.flash_ctrl_ro.768623163 |
|
|
Mar 07 03:02:11 PM PST 24 |
Mar 07 03:04:08 PM PST 24 |
968698800 ps |
| T1134 |
/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3320091724 |
|
|
Mar 07 03:11:36 PM PST 24 |
Mar 07 03:12:07 PM PST 24 |
31755400 ps |
| T1135 |
/workspace/coverage/default/0.flash_ctrl_otp_reset.3221062416 |
|
|
Mar 07 03:01:48 PM PST 24 |
Mar 07 03:04:06 PM PST 24 |
71983100 ps |
| T51 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.272683368 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 01:07:10 PM PST 24 |
3366171800 ps |
| T1136 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.251758469 |
|
|
Mar 07 12:59:25 PM PST 24 |
Mar 07 12:59:41 PM PST 24 |
43533400 ps |
| T52 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1664999953 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 01:00:01 PM PST 24 |
177280300 ps |
| T53 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1999957959 |
|
|
Mar 07 12:59:33 PM PST 24 |
Mar 07 12:59:50 PM PST 24 |
22000500 ps |
| T1137 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2557760582 |
|
|
Mar 07 12:59:21 PM PST 24 |
Mar 07 12:59:34 PM PST 24 |
22066400 ps |
| T264 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1828950581 |
|
|
Mar 07 12:59:15 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
28021500 ps |
| T187 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.807258542 |
|
|
Mar 07 12:59:12 PM PST 24 |
Mar 07 12:59:31 PM PST 24 |
775465100 ps |
| T260 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.720490832 |
|
|
Mar 07 12:59:18 PM PST 24 |
Mar 07 01:00:21 PM PST 24 |
2536187100 ps |
| T219 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3069757832 |
|
|
Mar 07 12:59:08 PM PST 24 |
Mar 07 12:59:53 PM PST 24 |
127751600 ps |
| T261 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1020928511 |
|
|
Mar 07 12:59:08 PM PST 24 |
Mar 07 12:59:46 PM PST 24 |
623589500 ps |
| T253 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.327625070 |
|
|
Mar 07 12:59:13 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
383047000 ps |
| T262 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4249203199 |
|
|
Mar 07 12:59:07 PM PST 24 |
Mar 07 12:59:25 PM PST 24 |
90135600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2208058234 |
|
|
Mar 07 12:59:05 PM PST 24 |
Mar 07 12:59:19 PM PST 24 |
17087400 ps |
| T188 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3315670940 |
|
|
Mar 07 12:59:42 PM PST 24 |
Mar 07 01:00:00 PM PST 24 |
248773100 ps |
| T216 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3254663576 |
|
|
Mar 07 12:59:06 PM PST 24 |
Mar 07 12:59:25 PM PST 24 |
101005300 ps |
| T263 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2700508595 |
|
|
Mar 07 12:59:08 PM PST 24 |
Mar 07 12:59:29 PM PST 24 |
301293600 ps |
| T327 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2593860810 |
|
|
Mar 07 12:59:36 PM PST 24 |
Mar 07 12:59:49 PM PST 24 |
23520800 ps |
| T326 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2357008819 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 01:00:24 PM PST 24 |
9896532800 ps |
| T328 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1361564833 |
|
|
Mar 07 12:59:39 PM PST 24 |
Mar 07 12:59:53 PM PST 24 |
119671200 ps |
| T1139 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3286557276 |
|
|
Mar 07 12:59:17 PM PST 24 |
Mar 07 12:59:53 PM PST 24 |
328063500 ps |
| T330 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3547035132 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 12:59:48 PM PST 24 |
44512800 ps |
| T217 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3659330206 |
|
|
Mar 07 12:59:46 PM PST 24 |
Mar 07 01:00:06 PM PST 24 |
100314600 ps |
| T349 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2767461779 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 12:59:49 PM PST 24 |
797349000 ps |
| T1140 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.806753898 |
|
|
Mar 07 12:59:17 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
142660800 ps |
| T233 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1138432461 |
|
|
Mar 07 12:59:36 PM PST 24 |
Mar 07 01:07:15 PM PST 24 |
686439700 ps |
| T230 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.215311287 |
|
|
Mar 07 12:59:15 PM PST 24 |
Mar 07 12:59:32 PM PST 24 |
50610800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3106212886 |
|
|
Mar 07 12:59:22 PM PST 24 |
Mar 07 12:59:38 PM PST 24 |
12064300 ps |
| T331 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.778193815 |
|
|
Mar 07 12:59:06 PM PST 24 |
Mar 07 12:59:20 PM PST 24 |
31560700 ps |
| T1142 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3838183318 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:36 PM PST 24 |
46010600 ps |
| T329 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4036495919 |
|
|
Mar 07 12:59:11 PM PST 24 |
Mar 07 12:59:24 PM PST 24 |
16124700 ps |
| T1143 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3021769704 |
|
|
Mar 07 12:59:17 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
51063500 ps |
| T336 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2237268514 |
|
|
Mar 07 12:59:24 PM PST 24 |
Mar 07 12:59:38 PM PST 24 |
14676800 ps |
| T1144 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4078151198 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 12:59:45 PM PST 24 |
18833800 ps |
| T1145 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2187879620 |
|
|
Mar 07 12:59:18 PM PST 24 |
Mar 07 12:59:52 PM PST 24 |
121965600 ps |
| T218 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.948358963 |
|
|
Mar 07 12:59:10 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
245614700 ps |
| T1146 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1318295059 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:30 PM PST 24 |
22468600 ps |
| T332 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.818714343 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 12:59:45 PM PST 24 |
70114000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2986195362 |
|
|
Mar 07 12:59:22 PM PST 24 |
Mar 07 12:59:40 PM PST 24 |
90900800 ps |
| T220 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1347466115 |
|
|
Mar 07 12:59:18 PM PST 24 |
Mar 07 12:59:36 PM PST 24 |
56715700 ps |
| T1148 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2439098465 |
|
|
Mar 07 12:59:01 PM PST 24 |
Mar 07 12:59:15 PM PST 24 |
54282200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1521181346 |
|
|
Mar 07 12:59:04 PM PST 24 |
Mar 07 12:59:17 PM PST 24 |
64078800 ps |
| T231 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1409153953 |
|
|
Mar 07 12:59:42 PM PST 24 |
Mar 07 12:59:57 PM PST 24 |
246499000 ps |
| T1150 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1778891824 |
|
|
Mar 07 12:59:11 PM PST 24 |
Mar 07 12:59:27 PM PST 24 |
16189400 ps |
| T1151 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1452990824 |
|
|
Mar 07 12:59:12 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
12636500 ps |
| T221 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1602516368 |
|
|
Mar 07 12:59:33 PM PST 24 |
Mar 07 12:59:52 PM PST 24 |
92965900 ps |
| T1152 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4071617437 |
|
|
Mar 07 12:59:40 PM PST 24 |
Mar 07 12:59:56 PM PST 24 |
65977700 ps |
| T1153 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1420278272 |
|
|
Mar 07 12:59:28 PM PST 24 |
Mar 07 12:59:42 PM PST 24 |
24363000 ps |
| T333 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.390232520 |
|
|
Mar 07 12:59:41 PM PST 24 |
Mar 07 12:59:55 PM PST 24 |
42179000 ps |
| T339 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3385197819 |
|
|
Mar 07 12:59:48 PM PST 24 |
Mar 07 01:00:02 PM PST 24 |
26832100 ps |
| T1154 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1893134686 |
|
|
Mar 07 12:59:05 PM PST 24 |
Mar 07 12:59:22 PM PST 24 |
121168000 ps |
| T340 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3694231242 |
|
|
Mar 07 12:59:50 PM PST 24 |
Mar 07 01:00:04 PM PST 24 |
125957900 ps |
| T1155 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2884966991 |
|
|
Mar 07 12:59:16 PM PST 24 |
Mar 07 12:59:30 PM PST 24 |
30182500 ps |
| T1156 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.224085804 |
|
|
Mar 07 12:59:13 PM PST 24 |
Mar 07 12:59:29 PM PST 24 |
22669700 ps |
| T301 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.946936711 |
|
|
Mar 07 12:59:08 PM PST 24 |
Mar 07 12:59:50 PM PST 24 |
2656236800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3416869065 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 12:59:47 PM PST 24 |
89953600 ps |
| T232 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3034609500 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:34 PM PST 24 |
109757900 ps |
| T256 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3998246563 |
|
|
Mar 07 12:59:07 PM PST 24 |
Mar 07 01:14:02 PM PST 24 |
3420133400 ps |
| T1158 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4049898638 |
|
|
Mar 07 12:59:10 PM PST 24 |
Mar 07 12:59:27 PM PST 24 |
44352700 ps |
| T1159 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2681664999 |
|
|
Mar 07 12:59:26 PM PST 24 |
Mar 07 12:59:40 PM PST 24 |
53118100 ps |
| T1160 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2021433945 |
|
|
Mar 07 12:59:20 PM PST 24 |
Mar 07 12:59:38 PM PST 24 |
167452000 ps |
| T1161 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3455601255 |
|
|
Mar 07 12:59:42 PM PST 24 |
Mar 07 12:59:55 PM PST 24 |
56952200 ps |
| T1162 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.89451405 |
|
|
Mar 07 12:59:22 PM PST 24 |
Mar 07 12:59:36 PM PST 24 |
48224600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.843760003 |
|
|
Mar 07 12:59:41 PM PST 24 |
Mar 07 12:59:54 PM PST 24 |
30873900 ps |
| T274 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1442827406 |
|
|
Mar 07 12:59:29 PM PST 24 |
Mar 07 01:12:15 PM PST 24 |
988092600 ps |
| T1164 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3056959974 |
|
|
Mar 07 12:59:06 PM PST 24 |
Mar 07 12:59:23 PM PST 24 |
60928200 ps |
| T268 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1407873671 |
|
|
Mar 07 12:59:24 PM PST 24 |
Mar 07 12:59:40 PM PST 24 |
31972100 ps |
| T1165 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2000183367 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 12:59:48 PM PST 24 |
48446400 ps |
| T1166 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1104536748 |
|
|
Mar 07 12:59:07 PM PST 24 |
Mar 07 12:59:37 PM PST 24 |
28386700 ps |
| T1167 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.105362995 |
|
|
Mar 07 12:59:11 PM PST 24 |
Mar 07 12:59:27 PM PST 24 |
22723300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.359022419 |
|
|
Mar 07 12:59:27 PM PST 24 |
Mar 07 12:59:43 PM PST 24 |
54013600 ps |
| T1169 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.196803549 |
|
|
Mar 07 12:59:37 PM PST 24 |
Mar 07 12:59:51 PM PST 24 |
18066500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2827609422 |
|
|
Mar 07 12:59:57 PM PST 24 |
Mar 07 01:00:12 PM PST 24 |
23427500 ps |
| T1171 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1636097913 |
|
|
Mar 07 12:59:45 PM PST 24 |
Mar 07 12:59:59 PM PST 24 |
29816300 ps |
| T271 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3426127120 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 01:07:05 PM PST 24 |
266575300 ps |
| T269 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3770103377 |
|
|
Mar 07 12:59:25 PM PST 24 |
Mar 07 12:59:42 PM PST 24 |
192304500 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2047421313 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 01:00:01 PM PST 24 |
19078400 ps |
| T341 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3343581964 |
|
|
Mar 07 12:59:20 PM PST 24 |
Mar 07 01:12:07 PM PST 24 |
1432730500 ps |
| T265 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.994695829 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 12:59:54 PM PST 24 |
804030900 ps |
| T1173 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.48980229 |
|
|
Mar 07 12:59:05 PM PST 24 |
Mar 07 12:59:19 PM PST 24 |
55179600 ps |
| T1174 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.205697753 |
|
|
Mar 07 12:59:18 PM PST 24 |
Mar 07 12:59:32 PM PST 24 |
53491800 ps |
| T307 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1938869808 |
|
|
Mar 07 12:59:11 PM PST 24 |
Mar 07 12:59:27 PM PST 24 |
36627400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.130561886 |
|
|
Mar 07 12:59:09 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
87933800 ps |
| T1176 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4134610723 |
|
|
Mar 07 12:59:44 PM PST 24 |
Mar 07 12:59:59 PM PST 24 |
21554800 ps |
| T1177 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.4076032835 |
|
|
Mar 07 12:59:13 PM PST 24 |
Mar 07 12:59:27 PM PST 24 |
50007700 ps |
| T344 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4065498567 |
|
|
Mar 07 12:59:26 PM PST 24 |
Mar 07 01:05:54 PM PST 24 |
649124600 ps |
| T1178 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3181762474 |
|
|
Mar 07 12:59:36 PM PST 24 |
Mar 07 12:59:49 PM PST 24 |
20640800 ps |
| T270 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2609305021 |
|
|
Mar 07 12:59:19 PM PST 24 |
Mar 07 12:59:40 PM PST 24 |
504653600 ps |
| T342 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3314197184 |
|
|
Mar 07 12:59:40 PM PST 24 |
Mar 07 01:14:36 PM PST 24 |
2446123600 ps |
| T1179 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1456668371 |
|
|
Mar 07 12:59:30 PM PST 24 |
Mar 07 12:59:43 PM PST 24 |
17577000 ps |
| T1180 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3705754716 |
|
|
Mar 07 12:59:28 PM PST 24 |
Mar 07 12:59:47 PM PST 24 |
216362600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2978343517 |
|
|
Mar 07 12:59:09 PM PST 24 |
Mar 07 12:59:22 PM PST 24 |
16526400 ps |
| T1182 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2121823893 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 12:59:48 PM PST 24 |
30740900 ps |
| T1183 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1883997410 |
|
|
Mar 07 12:59:09 PM PST 24 |
Mar 07 12:59:23 PM PST 24 |
16676400 ps |
| T1184 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3751257600 |
|
|
Mar 07 12:59:06 PM PST 24 |
Mar 07 12:59:25 PM PST 24 |
89314100 ps |
| T1185 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.357399128 |
|
|
Mar 07 12:59:29 PM PST 24 |
Mar 07 12:59:45 PM PST 24 |
32409900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4060027553 |
|
|
Mar 07 12:59:13 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
17951000 ps |
| T1187 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1661987847 |
|
|
Mar 07 12:59:22 PM PST 24 |
Mar 07 12:59:38 PM PST 24 |
11047700 ps |
| T306 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.405226485 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:36 PM PST 24 |
69105900 ps |
| T345 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.586653837 |
|
|
Mar 07 12:59:33 PM PST 24 |
Mar 07 01:14:28 PM PST 24 |
1360766600 ps |
| T1188 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.925974327 |
|
|
Mar 07 12:59:17 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
13214000 ps |
| T302 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4101009877 |
|
|
Mar 07 12:59:06 PM PST 24 |
Mar 07 12:59:48 PM PST 24 |
2382569100 ps |
| T1189 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2225660731 |
|
|
Mar 07 12:59:19 PM PST 24 |
Mar 07 12:59:34 PM PST 24 |
16926600 ps |
| T303 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2791057688 |
|
|
Mar 07 12:59:24 PM PST 24 |
Mar 07 12:59:43 PM PST 24 |
548415000 ps |
| T275 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1927644076 |
|
|
Mar 07 12:59:04 PM PST 24 |
Mar 07 12:59:26 PM PST 24 |
60118500 ps |
| T1190 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3874987906 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 12:59:47 PM PST 24 |
12800700 ps |
| T1191 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.726437787 |
|
|
Mar 07 12:59:43 PM PST 24 |
Mar 07 12:59:56 PM PST 24 |
49477600 ps |
| T276 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1744579088 |
|
|
Mar 07 12:59:13 PM PST 24 |
Mar 07 12:59:30 PM PST 24 |
75903900 ps |
| T343 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.790371349 |
|
|
Mar 07 12:59:18 PM PST 24 |
Mar 07 01:05:41 PM PST 24 |
748682200 ps |
| T304 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3550389465 |
|
|
Mar 07 12:59:16 PM PST 24 |
Mar 07 01:00:07 PM PST 24 |
6556185700 ps |
| T1192 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3774308454 |
|
|
Mar 07 12:59:33 PM PST 24 |
Mar 07 12:59:49 PM PST 24 |
13070400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1476189198 |
|
|
Mar 07 12:59:04 PM PST 24 |
Mar 07 12:59:17 PM PST 24 |
18571500 ps |
| T1194 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2302957999 |
|
|
Mar 07 12:59:49 PM PST 24 |
Mar 07 01:00:06 PM PST 24 |
24944200 ps |
| T1195 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.694823706 |
|
|
Mar 07 12:59:09 PM PST 24 |
Mar 07 12:59:23 PM PST 24 |
41787400 ps |
| T1196 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.15953040 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 12:59:48 PM PST 24 |
28712800 ps |
| T1197 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.109715354 |
|
|
Mar 07 12:59:23 PM PST 24 |
Mar 07 12:59:37 PM PST 24 |
15172700 ps |
| T1198 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2973191563 |
|
|
Mar 07 12:59:22 PM PST 24 |
Mar 07 12:59:38 PM PST 24 |
41534700 ps |
| T1199 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1267963475 |
|
|
Mar 07 12:59:46 PM PST 24 |
Mar 07 12:59:59 PM PST 24 |
54838800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3487336976 |
|
|
Mar 07 12:59:42 PM PST 24 |
Mar 07 12:59:59 PM PST 24 |
73651700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1911183418 |
|
|
Mar 07 12:59:32 PM PST 24 |
Mar 07 12:59:46 PM PST 24 |
19055200 ps |
| T235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2982731100 |
|
|
Mar 07 12:59:19 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
19031700 ps |
| T272 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2953710262 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:32 PM PST 24 |
66666100 ps |
| T1202 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.626895839 |
|
|
Mar 07 12:59:20 PM PST 24 |
Mar 07 12:59:34 PM PST 24 |
25807900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.554960985 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 12:59:52 PM PST 24 |
309709400 ps |
| T273 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.813041709 |
|
|
Mar 07 12:59:09 PM PST 24 |
Mar 07 01:14:20 PM PST 24 |
2704403100 ps |
| T347 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1579102163 |
|
|
Mar 07 12:59:48 PM PST 24 |
Mar 07 01:15:08 PM PST 24 |
1383911800 ps |
| T1204 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.23001354 |
|
|
Mar 07 12:59:42 PM PST 24 |
Mar 07 12:59:58 PM PST 24 |
66180800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1088847864 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 12:59:48 PM PST 24 |
44951500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3141830438 |
|
|
Mar 07 12:59:35 PM PST 24 |
Mar 07 12:59:51 PM PST 24 |
113051100 ps |
| T1207 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4258736428 |
|
|
Mar 07 12:59:48 PM PST 24 |
Mar 07 01:00:02 PM PST 24 |
69136700 ps |
| T1208 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.94964179 |
|
|
Mar 07 12:59:05 PM PST 24 |
Mar 07 12:59:24 PM PST 24 |
140784700 ps |
| T1209 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.785157628 |
|
|
Mar 07 12:59:52 PM PST 24 |
Mar 07 01:00:06 PM PST 24 |
16909100 ps |
| T1210 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1890242354 |
|
|
Mar 07 12:59:07 PM PST 24 |
Mar 07 12:59:25 PM PST 24 |
98726400 ps |
| T1211 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3769193350 |
|
|
Mar 07 12:59:15 PM PST 24 |
Mar 07 12:59:52 PM PST 24 |
2314552800 ps |
| T305 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1212965013 |
|
|
Mar 07 12:59:09 PM PST 24 |
Mar 07 12:59:53 PM PST 24 |
99539100 ps |
| T308 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1386985493 |
|
|
Mar 07 12:59:09 PM PST 24 |
Mar 07 12:59:27 PM PST 24 |
268495100 ps |
| T309 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2666813237 |
|
|
Mar 07 12:59:07 PM PST 24 |
Mar 07 12:59:26 PM PST 24 |
802313600 ps |
| T310 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3023817947 |
|
|
Mar 07 12:59:04 PM PST 24 |
Mar 07 01:00:04 PM PST 24 |
5604537500 ps |
| T1212 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1155929812 |
|
|
Mar 07 12:59:16 PM PST 24 |
Mar 07 12:59:29 PM PST 24 |
48758700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.808431713 |
|
|
Mar 07 12:59:06 PM PST 24 |
Mar 07 12:59:22 PM PST 24 |
57412900 ps |
| T236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.454522545 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:27 PM PST 24 |
43564700 ps |
| T1214 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2003020750 |
|
|
Mar 07 12:59:20 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
14875800 ps |
| T1215 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2626032240 |
|
|
Mar 07 12:59:43 PM PST 24 |
Mar 07 12:59:59 PM PST 24 |
64231000 ps |
| T1216 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3643915538 |
|
|
Mar 07 12:59:10 PM PST 24 |
Mar 07 12:59:29 PM PST 24 |
417721900 ps |
| T237 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1076353887 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
18615700 ps |
| T1217 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.303725816 |
|
|
Mar 07 12:59:10 PM PST 24 |
Mar 07 12:59:26 PM PST 24 |
37787600 ps |
| T1218 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.817606718 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
101141400 ps |
| T1219 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1850933838 |
|
|
Mar 07 12:59:45 PM PST 24 |
Mar 07 12:59:59 PM PST 24 |
26227800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.4051600593 |
|
|
Mar 07 12:59:44 PM PST 24 |
Mar 07 01:00:04 PM PST 24 |
144813800 ps |
| T1221 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1707667015 |
|
|
Mar 07 12:59:15 PM PST 24 |
Mar 07 12:59:32 PM PST 24 |
158893700 ps |
| T1222 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2404256429 |
|
|
Mar 07 12:59:13 PM PST 24 |
Mar 07 12:59:26 PM PST 24 |
13924800 ps |
| T348 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3011077394 |
|
|
Mar 07 12:59:20 PM PST 24 |
Mar 07 01:11:57 PM PST 24 |
354655600 ps |
| T311 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.64052371 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 01:14:22 PM PST 24 |
1660941500 ps |
| T312 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2692752920 |
|
|
Mar 07 12:59:35 PM PST 24 |
Mar 07 12:59:55 PM PST 24 |
876127200 ps |
| T313 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2398052776 |
|
|
Mar 07 12:59:10 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
224848100 ps |
| T1223 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2197473732 |
|
|
Mar 07 12:59:49 PM PST 24 |
Mar 07 01:00:03 PM PST 24 |
50276400 ps |
| T1224 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3294666248 |
|
|
Mar 07 12:59:34 PM PST 24 |
Mar 07 12:59:48 PM PST 24 |
37225500 ps |
| T266 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2520642251 |
|
|
Mar 07 12:59:12 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
43429400 ps |
| T1225 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1555647634 |
|
|
Mar 07 12:59:10 PM PST 24 |
Mar 07 12:59:28 PM PST 24 |
48726400 ps |
| T1226 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.531338284 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
162719200 ps |
| T1227 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1418673683 |
|
|
Mar 07 12:59:16 PM PST 24 |
Mar 07 12:59:34 PM PST 24 |
122506900 ps |
| T1228 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3092538864 |
|
|
Mar 07 12:59:16 PM PST 24 |
Mar 07 12:59:47 PM PST 24 |
197445900 ps |
| T1229 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.189578109 |
|
|
Mar 07 12:59:16 PM PST 24 |
Mar 07 12:59:32 PM PST 24 |
13572600 ps |
| T1230 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3488674523 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 01:12:05 PM PST 24 |
672084600 ps |
| T238 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1912530317 |
|
|
Mar 07 12:59:06 PM PST 24 |
Mar 07 12:59:20 PM PST 24 |
17392100 ps |
| T1231 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.201949457 |
|
|
Mar 07 12:59:38 PM PST 24 |
Mar 07 12:59:53 PM PST 24 |
80276900 ps |
| T267 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.320975761 |
|
|
Mar 07 12:59:09 PM PST 24 |
Mar 07 12:59:25 PM PST 24 |
149787600 ps |
| T1232 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.926693253 |
|
|
Mar 07 12:59:23 PM PST 24 |
Mar 07 12:59:39 PM PST 24 |
14442300 ps |
| T1233 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.537740711 |
|
|
Mar 07 12:59:30 PM PST 24 |
Mar 07 12:59:44 PM PST 24 |
183060100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2888543143 |
|
|
Mar 07 12:59:20 PM PST 24 |
Mar 07 01:07:01 PM PST 24 |
1704145400 ps |
| T1235 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.951090621 |
|
|
Mar 07 12:59:38 PM PST 24 |
Mar 07 12:59:52 PM PST 24 |
24099100 ps |
| T1236 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3087888071 |
|
|
Mar 07 12:59:43 PM PST 24 |
Mar 07 01:00:02 PM PST 24 |
228931200 ps |
| T1237 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1160675814 |
|
|
Mar 07 12:59:46 PM PST 24 |
Mar 07 01:00:00 PM PST 24 |
25110000 ps |
| T1238 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3291697224 |
|
|
Mar 07 12:59:17 PM PST 24 |
Mar 07 12:59:33 PM PST 24 |
12832700 ps |
| T1239 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1847962913 |
|
|
Mar 07 12:59:45 PM PST 24 |
Mar 07 12:59:59 PM PST 24 |
60725000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.319211227 |
|
|
Mar 07 12:59:15 PM PST 24 |
Mar 07 12:59:32 PM PST 24 |
73184400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4010420891 |
|
|
Mar 07 12:59:07 PM PST 24 |
Mar 07 12:59:25 PM PST 24 |
111141700 ps |
| T1242 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3085041355 |
|
|
Mar 07 12:59:31 PM PST 24 |
Mar 07 12:59:48 PM PST 24 |
42498600 ps |
| T1243 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4088802210 |
|
|
Mar 07 12:59:13 PM PST 24 |
Mar 07 12:59:26 PM PST 24 |
14362800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1260059873 |
|
|
Mar 07 12:59:12 PM PST 24 |
Mar 07 12:59:29 PM PST 24 |
64698600 ps |
| T1245 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2611274681 |
|
|
Mar 07 12:59:06 PM PST 24 |
Mar 07 12:59:21 PM PST 24 |
20765700 ps |
| T1246 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2123831083 |
|
|
Mar 07 12:59:48 PM PST 24 |
Mar 07 01:00:07 PM PST 24 |
311080400 ps |
| T1247 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1824915234 |
|
|
Mar 07 12:59:36 PM PST 24 |
Mar 07 12:59:49 PM PST 24 |
29364400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2084621446 |
|
|
Mar 07 12:59:32 PM PST 24 |
Mar 07 12:59:47 PM PST 24 |
383903900 ps |
| T1249 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.97734493 |
|
|
Mar 07 12:59:12 PM PST 24 |
Mar 07 01:00:33 PM PST 24 |
9251770300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1817498891 |
|
|
Mar 07 12:59:38 PM PST 24 |
Mar 07 12:59:56 PM PST 24 |
25044500 ps |
| T346 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3648431821 |
|
|
Mar 07 12:59:19 PM PST 24 |
Mar 07 01:07:01 PM PST 24 |
2798367700 ps |
| T1251 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.82056175 |
|
|
Mar 07 12:59:14 PM PST 24 |
Mar 07 12:59:32 PM PST 24 |
50255900 ps |