Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	314073	1		T1	2		T2	1		T3	22
all_values[1]	314073	1		T1	2		T2	1		T3	22
all_values[2]	314073	1		T1	2		T2	1		T3	22
all_values[3]	314073	1		T1	2		T2	1		T3	22
all_values[4]	314073	1		T1	2		T2	1		T3	22
all_values[5]	314073	1		T1	2		T2	1		T3	22

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	634619	1		T1	12		T2	6		T3	132
auto[1]	1249819	1		T4	4356		T6	9400		T20	9852

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	924715	1		T1	7		T2	4		T3	81
auto[1]	959723	1		T1	5		T2	2		T3	51

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	313923	1		T1	2		T2	1		T3	22
all_values[0]	auto[1]	auto[1]	150	1		T244	1		T245	5		T246	1
all_values[1]	auto[0]	auto[1]	313911	1		T1	2		T2	1		T3	22
all_values[1]	auto[1]	auto[1]	162	1		T245	5		T246	2		T310	6
all_values[2]	auto[0]	auto[0]	1647	1		T1	2		T2	1		T3	22
all_values[2]	auto[0]	auto[1]	60	1		T246	2		T310	4		T311	1
all_values[2]	auto[1]	auto[0]	312307	1		T4	1089		T6	2350		T20	2463
all_values[2]	auto[1]	auto[1]	59	1		T245	3		T246	1		T310	1
all_values[3]	auto[0]	auto[0]	1643	1		T1	2		T2	1		T3	22
all_values[3]	auto[0]	auto[1]	63	1		T244	1		T245	1		T246	2
all_values[3]	auto[1]	auto[0]	80160	1		T4	1089		T6	1158		T20	821
all_values[3]	auto[1]	auto[1]	232207	1		T6	1192		T20	1642		T37	12561
all_values[4]	auto[0]	auto[0]	1140	1		T1	1		T2	1		T3	15
all_values[4]	auto[0]	auto[1]	537	1		T1	1		T3	7		T7	3
all_values[4]	auto[1]	auto[0]	213962	1		T4	1		T6	1158		T20	1642
all_values[4]	auto[1]	auto[1]	98434	1		T4	1088		T6	1192		T20	821
all_values[5]	auto[0]	auto[0]	1544	1		T1	2		T2	1		T3	22
all_values[5]	auto[0]	auto[1]	151	1		T7	3		T38	1		T39	1
all_values[5]	auto[1]	auto[0]	312312	1		T4	1089		T6	2350		T20	2463
all_values[5]	auto[1]	auto[1]	66	1		T245	4		T246	2		T310	2