Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1202 |
1 |
|
T3 |
2 |
|
T42 |
1 |
|
T168 |
1 |
| others[1] |
1198 |
1 |
|
T3 |
3 |
|
T6 |
1 |
|
T18 |
1 |
| others[2] |
1208 |
1 |
|
T3 |
3 |
|
T19 |
10 |
|
T21 |
19 |
| others[3] |
2118 |
1 |
|
T3 |
4 |
|
T19 |
23 |
|
T21 |
33 |
| false |
622 |
1 |
|
T4 |
1 |
|
T19 |
3 |
|
T21 |
2 |
| true |
419 |
1 |
|
T7 |
5 |
|
T17 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T3 |
3 |
|
T21 |
7 |
|
T22 |
4 |
| others[1] |
96 |
1 |
|
T3 |
1 |
|
T42 |
1 |
|
T21 |
3 |
| others[2] |
94 |
1 |
|
T3 |
3 |
|
T21 |
3 |
|
T22 |
4 |
| others[3] |
179 |
1 |
|
T3 |
4 |
|
T7 |
1 |
|
T21 |
8 |
| false |
54 |
1 |
|
T3 |
1 |
|
T21 |
3 |
|
T22 |
1 |
| true |
6245 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T21 |
10 |
|
T22 |
13 |
|
T37 |
1 |
| others[1] |
233 |
1 |
|
T21 |
19 |
|
T22 |
10 |
|
T23 |
9 |
| others[2] |
261 |
1 |
|
T3 |
3 |
|
T21 |
8 |
|
T22 |
5 |
| others[3] |
365 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T21 |
10 |
| false |
119 |
1 |
|
T21 |
6 |
|
T22 |
8 |
|
T23 |
7 |
| true |
5585 |
1 |
|
T3 |
8 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1123 |
1 |
|
T3 |
4 |
|
T19 |
18 |
|
T21 |
22 |
| others[1] |
999 |
1 |
|
T3 |
3 |
|
T18 |
1 |
|
T19 |
13 |
| others[2] |
1009 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
| others[3] |
1730 |
1 |
|
T3 |
3 |
|
T19 |
10 |
|
T21 |
35 |
| false |
570 |
1 |
|
T3 |
1 |
|
T19 |
4 |
|
T21 |
10 |
| true |
1336 |
1 |
|
T6 |
1 |
|
T7 |
4 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T21 |
6 |
|
T78 |
1 |
|
T22 |
6 |
| others[1] |
240 |
1 |
|
T3 |
1 |
|
T21 |
12 |
|
T22 |
14 |
| others[2] |
218 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T17 |
1 |
| others[3] |
355 |
1 |
|
T3 |
3 |
|
T7 |
1 |
|
T42 |
1 |
| false |
123 |
1 |
|
T7 |
1 |
|
T21 |
7 |
|
T78 |
1 |
| true |
5599 |
1 |
|
T3 |
7 |
|
T4 |
1 |
|
T7 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T3 |
1 |
|
T21 |
11 |
|
T22 |
5 |
| others[1] |
221 |
1 |
|
T3 |
1 |
|
T21 |
11 |
|
T22 |
13 |
| others[2] |
186 |
1 |
|
T42 |
1 |
|
T21 |
10 |
|
T22 |
8 |
| others[3] |
340 |
1 |
|
T3 |
3 |
|
T21 |
18 |
|
T78 |
2 |
| false |
116 |
1 |
|
T3 |
1 |
|
T21 |
7 |
|
T22 |
6 |
| true |
5660 |
1 |
|
T3 |
6 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T7 |
1 |
|
T42 |
1 |
|
T18 |
1 |
| others[1] |
1189 |
1 |
|
T3 |
2 |
|
T19 |
8 |
|
T21 |
25 |
| others[2] |
1209 |
1 |
|
T3 |
2 |
|
T19 |
9 |
|
T21 |
24 |
| others[3] |
2122 |
1 |
|
T3 |
4 |
|
T4 |
1 |
|
T19 |
24 |
| false |
606 |
1 |
|
T3 |
4 |
|
T168 |
1 |
|
T19 |
2 |
| true |
423 |
1 |
|
T6 |
1 |
|
T7 |
4 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1200 |
1 |
|
T3 |
1 |
|
T19 |
10 |
|
T43 |
1 |
| others[1] |
1216 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T42 |
1 |
| others[2] |
1223 |
1 |
|
T3 |
4 |
|
T6 |
1 |
|
T18 |
1 |
| others[3] |
2070 |
1 |
|
T3 |
1 |
|
T168 |
1 |
|
T19 |
13 |
| false |
633 |
1 |
|
T3 |
4 |
|
T19 |
4 |
|
T21 |
16 |
| true |
425 |
1 |
|
T7 |
5 |
|
T17 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T3 |
5 |
|
T42 |
1 |
|
T21 |
3 |
| others[1] |
99 |
1 |
|
T3 |
4 |
|
T21 |
6 |
|
T22 |
4 |
| others[2] |
98 |
1 |
|
T3 |
1 |
|
T21 |
5 |
|
T78 |
1 |
| others[3] |
165 |
1 |
|
T7 |
1 |
|
T21 |
6 |
|
T78 |
1 |
| false |
56 |
1 |
|
T3 |
2 |
|
T21 |
3 |
|
T22 |
1 |
| true |
6249 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
266 |
1 |
|
T3 |
1 |
|
T42 |
1 |
|
T21 |
17 |
| others[1] |
211 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T21 |
11 |
| others[2] |
208 |
1 |
|
T27 |
1 |
|
T21 |
6 |
|
T22 |
8 |
| others[3] |
409 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T21 |
22 |
| false |
120 |
1 |
|
T21 |
7 |
|
T22 |
3 |
|
T23 |
4 |
| true |
5553 |
1 |
|
T3 |
9 |
|
T4 |
1 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1085 |
1 |
|
T3 |
3 |
|
T42 |
1 |
|
T168 |
1 |
| others[1] |
1075 |
1 |
|
T3 |
3 |
|
T7 |
1 |
|
T12 |
1 |
| others[2] |
1005 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T19 |
6 |
| others[3] |
1749 |
1 |
|
T3 |
4 |
|
T4 |
1 |
|
T6 |
1 |
| false |
538 |
1 |
|
T19 |
4 |
|
T43 |
1 |
|
T21 |
6 |
| true |
1315 |
1 |
|
T7 |
2 |
|
T17 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T7 |
1 |
|
T21 |
7 |
|
T78 |
1 |
| others[1] |
205 |
1 |
|
T3 |
1 |
|
T27 |
1 |
|
T21 |
11 |
| others[2] |
234 |
1 |
|
T3 |
3 |
|
T21 |
4 |
|
T22 |
7 |
| others[3] |
379 |
1 |
|
T3 |
3 |
|
T7 |
2 |
|
T21 |
19 |
| false |
137 |
1 |
|
T7 |
1 |
|
T21 |
4 |
|
T22 |
10 |
| true |
5611 |
1 |
|
T3 |
5 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T3 |
3 |
|
T21 |
6 |
|
T22 |
7 |
| others[1] |
206 |
1 |
|
T21 |
4 |
|
T22 |
7 |
|
T23 |
13 |
| others[2] |
231 |
1 |
|
T3 |
2 |
|
T21 |
11 |
|
T78 |
1 |
| others[3] |
349 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T21 |
15 |
| false |
97 |
1 |
|
T21 |
3 |
|
T22 |
8 |
|
T23 |
8 |
| true |
5680 |
1 |
|
T3 |
5 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T3 |
3 |
|
T19 |
4 |
|
T43 |
1 |
| others[1] |
1223 |
1 |
|
T3 |
4 |
|
T19 |
14 |
|
T21 |
19 |
| others[2] |
1245 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T42 |
1 |
| others[3] |
2050 |
1 |
|
T3 |
3 |
|
T168 |
1 |
|
T19 |
18 |
| false |
585 |
1 |
|
T3 |
1 |
|
T27 |
1 |
|
T19 |
4 |
| true |
447 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T3 |
2 |
|
T18 |
1 |
|
T19 |
9 |
| others[1] |
1243 |
1 |
|
T3 |
2 |
|
T19 |
8 |
|
T21 |
14 |
| others[2] |
1239 |
1 |
|
T3 |
3 |
|
T42 |
1 |
|
T19 |
13 |
| others[3] |
2011 |
1 |
|
T3 |
3 |
|
T4 |
1 |
|
T6 |
1 |
| false |
644 |
1 |
|
T3 |
2 |
|
T19 |
5 |
|
T21 |
15 |
| true |
417 |
1 |
|
T7 |
5 |
|
T27 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T3 |
4 |
|
T21 |
2 |
|
T22 |
2 |
| others[1] |
118 |
1 |
|
T3 |
1 |
|
T21 |
4 |
|
T22 |
6 |
| others[2] |
94 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T21 |
1 |
| others[3] |
188 |
1 |
|
T3 |
5 |
|
T42 |
1 |
|
T21 |
11 |
| false |
49 |
1 |
|
T3 |
1 |
|
T21 |
3 |
|
T78 |
1 |
| true |
6207 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
192 |
1 |
|
T7 |
2 |
|
T21 |
7 |
|
T22 |
7 |
| others[1] |
237 |
1 |
|
T3 |
2 |
|
T21 |
11 |
|
T22 |
16 |
| others[2] |
224 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
2 |
| others[3] |
367 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T27 |
1 |
| false |
106 |
1 |
|
T21 |
4 |
|
T78 |
1 |
|
T22 |
6 |
| true |
5641 |
1 |
|
T3 |
7 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T42 |
1 |
| others[1] |
1023 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T12 |
1 |
| others[2] |
1014 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T19 |
14 |
| others[3] |
1716 |
1 |
|
T3 |
6 |
|
T6 |
1 |
|
T7 |
2 |
| false |
540 |
1 |
|
T3 |
3 |
|
T27 |
1 |
|
T19 |
5 |
| true |
1408 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T27 |
1 |
| others[1] |
230 |
1 |
|
T7 |
1 |
|
T21 |
12 |
|
T22 |
11 |
| others[2] |
223 |
1 |
|
T3 |
1 |
|
T21 |
13 |
|
T78 |
2 |
| others[3] |
371 |
1 |
|
T3 |
2 |
|
T21 |
13 |
|
T22 |
18 |
| false |
116 |
1 |
|
T7 |
1 |
|
T21 |
3 |
|
T22 |
3 |
| true |
5607 |
1 |
|
T3 |
8 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T42 |
1 |
|
T21 |
10 |
|
T22 |
9 |
| others[1] |
216 |
1 |
|
T3 |
1 |
|
T21 |
6 |
|
T22 |
10 |
| others[2] |
244 |
1 |
|
T21 |
11 |
|
T22 |
12 |
|
T357 |
1 |
| others[3] |
357 |
1 |
|
T3 |
2 |
|
T7 |
4 |
|
T21 |
11 |
| false |
108 |
1 |
|
T3 |
1 |
|
T21 |
8 |
|
T22 |
6 |
| true |
5640 |
1 |
|
T3 |
8 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T3 |
4 |
|
T17 |
1 |
|
T19 |
8 |
| others[1] |
1221 |
1 |
|
T3 |
1 |
|
T42 |
1 |
|
T19 |
8 |
| others[2] |
1205 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T19 |
11 |
| others[3] |
2028 |
1 |
|
T3 |
6 |
|
T4 |
1 |
|
T168 |
1 |
| false |
647 |
1 |
|
T19 |
9 |
|
T21 |
6 |
|
T22 |
14 |
| true |
449 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T168 |
1 |
| others[1] |
1159 |
1 |
|
T19 |
5 |
|
T21 |
18 |
|
T22 |
16 |
| others[2] |
1278 |
1 |
|
T3 |
5 |
|
T19 |
11 |
|
T21 |
18 |
| others[3] |
2012 |
1 |
|
T3 |
2 |
|
T42 |
1 |
|
T18 |
1 |
| false |
650 |
1 |
|
T3 |
4 |
|
T19 |
9 |
|
T21 |
11 |
| true |
424 |
1 |
|
T6 |
1 |
|
T7 |
5 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T3 |
3 |
|
T21 |
4 |
|
T22 |
5 |
| others[1] |
102 |
1 |
|
T3 |
1 |
|
T21 |
4 |
|
T78 |
1 |
| others[2] |
102 |
1 |
|
T3 |
2 |
|
T21 |
5 |
|
T22 |
2 |
| others[3] |
195 |
1 |
|
T3 |
5 |
|
T42 |
1 |
|
T21 |
8 |
| false |
46 |
1 |
|
T3 |
1 |
|
T21 |
2 |
|
T22 |
1 |
| true |
6214 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T21 |
15 |
| others[1] |
234 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T21 |
10 |
| others[2] |
226 |
1 |
|
T21 |
9 |
|
T22 |
12 |
|
T23 |
10 |
| others[3] |
406 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T27 |
1 |
| false |
117 |
1 |
|
T3 |
2 |
|
T21 |
3 |
|
T22 |
2 |
| true |
5543 |
1 |
|
T3 |
6 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
991 |
1 |
|
T3 |
3 |
|
T19 |
13 |
|
T21 |
19 |
| others[1] |
1029 |
1 |
|
T3 |
3 |
|
T7 |
1 |
|
T19 |
16 |
| others[2] |
1061 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T19 |
3 |
| others[3] |
1698 |
1 |
|
T3 |
3 |
|
T27 |
1 |
|
T18 |
1 |
| false |
595 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T42 |
1 |
| true |
1393 |
1 |
|
T6 |
1 |
|
T7 |
4 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T3 |
2 |
|
T21 |
11 |
|
T22 |
7 |
| others[1] |
234 |
1 |
|
T3 |
1 |
|
T21 |
18 |
|
T22 |
14 |
| others[2] |
207 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T21 |
8 |
| others[3] |
362 |
1 |
|
T21 |
12 |
|
T22 |
22 |
|
T103 |
1 |
| false |
118 |
1 |
|
T3 |
1 |
|
T21 |
3 |
|
T22 |
5 |
| true |
5607 |
1 |
|
T3 |
7 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T21 |
10 |
|
T22 |
9 |
|
T23 |
12 |
| others[1] |
191 |
1 |
|
T7 |
1 |
|
T21 |
7 |
|
T78 |
1 |
| others[2] |
217 |
1 |
|
T3 |
2 |
|
T7 |
2 |
|
T21 |
9 |
| others[3] |
362 |
1 |
|
T3 |
2 |
|
T7 |
2 |
|
T17 |
1 |
| false |
112 |
1 |
|
T21 |
5 |
|
T78 |
1 |
|
T22 |
4 |
| true |
5664 |
1 |
|
T3 |
8 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1212 |
1 |
|
T3 |
4 |
|
T19 |
11 |
|
T21 |
19 |
| others[1] |
1210 |
1 |
|
T3 |
4 |
|
T4 |
1 |
|
T19 |
8 |
| others[2] |
1206 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T168 |
1 |
| others[3] |
2045 |
1 |
|
T3 |
2 |
|
T19 |
20 |
|
T21 |
30 |
| false |
655 |
1 |
|
T7 |
1 |
|
T42 |
1 |
|
T19 |
5 |
| true |
439 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9 |
1 |
|
T146 |
1 |
|
T157 |
1 |
|
T358 |
1 |
| others[1] |
8 |
1 |
|
T11 |
1 |
|
T150 |
1 |
|
T359 |
1 |
| others[2] |
6 |
1 |
|
T90 |
1 |
|
T130 |
1 |
|
T152 |
1 |
| others[3] |
13 |
1 |
|
T11 |
1 |
|
T131 |
1 |
|
T360 |
1 |
| false |
2 |
1 |
|
T361 |
1 |
|
T362 |
1 |
|
- |
- |
| true |
41 |
1 |
|
T2 |
1 |
|
T65 |
2 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T223 |
1 |
|
T363 |
1 |
|
T364 |
1 |
| others[1] |
2 |
1 |
|
T365 |
1 |
|
T366 |
1 |
|
- |
- |
| others[2] |
1 |
1 |
|
T367 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
4 |
1 |
|
T368 |
1 |
|
T369 |
1 |
|
T370 |
1 |
| false |
6 |
1 |
|
T371 |
1 |
|
T372 |
1 |
|
T373 |
1 |
| true |
26 |
1 |
|
T34 |
1 |
|
T260 |
1 |
|
T374 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T375 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
1 |
1 |
|
T376 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
1 |
1 |
|
T377 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
2 |
1 |
|
T371 |
1 |
|
T378 |
1 |
|
- |
- |
| false |
8 |
1 |
|
T374 |
1 |
|
T368 |
1 |
|
T379 |
1 |
| true |
30 |
1 |
|
T34 |
1 |
|
T260 |
1 |
|
T223 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |