Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10255 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
8 |
| others[1] |
784 |
1 |
|
T3 |
1 |
|
T19 |
11 |
|
T21 |
20 |
| others[2] |
769 |
1 |
|
T1 |
1 |
|
T3 |
2 |
|
T4 |
1 |
| others[3] |
1290 |
1 |
|
T1 |
6 |
|
T3 |
1 |
|
T6 |
1 |
| false |
362 |
1 |
|
T19 |
9 |
|
T21 |
5 |
|
T87 |
1 |
| true |
550 |
1 |
|
T3 |
7 |
|
T7 |
5 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2439 |
1 |
|
T3 |
1 |
|
T5 |
40 |
|
T24 |
44 |
| others[1] |
2440 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T5 |
39 |
| others[2] |
2385 |
1 |
|
T3 |
3 |
|
T4 |
1 |
|
T7 |
1 |
| others[3] |
3989 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T5 |
47 |
| false |
1228 |
1 |
|
T3 |
2 |
|
T5 |
14 |
|
T24 |
7 |
| true |
1529 |
1 |
|
T1 |
8 |
|
T3 |
7 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9729 |
1 |
|
T2 |
2 |
|
T7 |
1 |
|
T5 |
174 |
| others[1] |
283 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T21 |
7 |
| others[2] |
274 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T168 |
1 |
| others[3] |
447 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T7 |
1 |
| false |
139 |
1 |
|
T1 |
1 |
|
T7 |
2 |
|
T21 |
12 |
| true |
3138 |
1 |
|
T1 |
6 |
|
T3 |
14 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9967 |
1 |
|
T2 |
2 |
|
T3 |
9 |
|
T5 |
174 |
| others[1] |
441 |
1 |
|
T3 |
5 |
|
T19 |
5 |
|
T21 |
13 |
| others[2] |
453 |
1 |
|
T1 |
4 |
|
T3 |
1 |
|
T7 |
1 |
| others[3] |
737 |
1 |
|
T3 |
4 |
|
T7 |
1 |
|
T19 |
7 |
| false |
233 |
1 |
|
T42 |
1 |
|
T27 |
1 |
|
T19 |
2 |
| true |
2179 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9722 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
174 |
| others[1] |
253 |
1 |
|
T3 |
2 |
|
T21 |
12 |
|
T22 |
7 |
| others[2] |
238 |
1 |
|
T7 |
1 |
|
T21 |
10 |
|
T22 |
9 |
| others[3] |
421 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T7 |
2 |
| false |
123 |
1 |
|
T27 |
1 |
|
T21 |
5 |
|
T22 |
6 |
| true |
3253 |
1 |
|
T1 |
8 |
|
T3 |
14 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9713 |
1 |
|
T2 |
2 |
|
T3 |
2 |
|
T5 |
174 |
| others[1] |
242 |
1 |
|
T3 |
2 |
|
T17 |
1 |
|
T21 |
10 |
| others[2] |
222 |
1 |
|
T3 |
2 |
|
T21 |
6 |
|
T22 |
12 |
| others[3] |
429 |
1 |
|
T3 |
2 |
|
T21 |
14 |
|
T78 |
1 |
| false |
133 |
1 |
|
T7 |
1 |
|
T21 |
6 |
|
T22 |
5 |
| true |
3271 |
1 |
|
T1 |
8 |
|
T3 |
11 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10286 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
8 |
| others[1] |
777 |
1 |
|
T1 |
1 |
|
T3 |
2 |
|
T19 |
13 |
| others[2] |
772 |
1 |
|
T1 |
2 |
|
T3 |
3 |
|
T4 |
1 |
| others[3] |
1253 |
1 |
|
T1 |
4 |
|
T3 |
2 |
|
T42 |
1 |
| false |
401 |
1 |
|
T3 |
1 |
|
T19 |
6 |
|
T21 |
9 |
| true |
521 |
1 |
|
T3 |
3 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10229 |
1 |
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
2 |
| others[1] |
790 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
| others[2] |
793 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
1 |
| others[3] |
1271 |
1 |
|
T1 |
2 |
|
T3 |
3 |
|
T168 |
1 |
| false |
368 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| true |
533 |
1 |
|
T3 |
4 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2494 |
1 |
|
T2 |
2 |
|
T3 |
3 |
|
T5 |
30 |
| others[1] |
2406 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
2 |
| others[2] |
2337 |
1 |
|
T3 |
2 |
|
T5 |
29 |
|
T42 |
1 |
| others[3] |
3946 |
1 |
|
T3 |
5 |
|
T7 |
1 |
|
T5 |
60 |
| false |
1285 |
1 |
|
T3 |
1 |
|
T5 |
21 |
|
T17 |
1 |
| true |
1516 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T7 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9733 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
| others[1] |
277 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T21 |
14 |
| others[2] |
285 |
1 |
|
T17 |
1 |
|
T21 |
12 |
|
T87 |
1 |
| others[3] |
444 |
1 |
|
T1 |
1 |
|
T3 |
4 |
|
T7 |
2 |
| false |
147 |
1 |
|
T1 |
1 |
|
T21 |
2 |
|
T22 |
3 |
| true |
3098 |
1 |
|
T1 |
4 |
|
T3 |
6 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9917 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
3 |
| others[1] |
427 |
1 |
|
T1 |
1 |
|
T3 |
2 |
|
T19 |
3 |
| others[2] |
447 |
1 |
|
T1 |
1 |
|
T3 |
3 |
|
T12 |
1 |
| others[3] |
731 |
1 |
|
T1 |
1 |
|
T3 |
4 |
|
T42 |
1 |
| false |
225 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T19 |
5 |
| true |
2237 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9724 |
1 |
|
T2 |
2 |
|
T3 |
2 |
|
T7 |
1 |
| others[1] |
232 |
1 |
|
T3 |
1 |
|
T27 |
1 |
|
T21 |
10 |
| others[2] |
250 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T21 |
4 |
| others[3] |
453 |
1 |
|
T6 |
1 |
|
T7 |
3 |
|
T21 |
17 |
| false |
113 |
1 |
|
T21 |
2 |
|
T78 |
1 |
|
T22 |
4 |
| true |
3212 |
1 |
|
T1 |
8 |
|
T3 |
7 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9702 |
1 |
|
T2 |
2 |
|
T3 |
2 |
|
T5 |
174 |
| others[1] |
241 |
1 |
|
T3 |
1 |
|
T21 |
9 |
|
T22 |
6 |
| others[2] |
273 |
1 |
|
T3 |
3 |
|
T43 |
1 |
|
T21 |
7 |
| others[3] |
422 |
1 |
|
T3 |
2 |
|
T42 |
1 |
|
T168 |
1 |
| false |
124 |
1 |
|
T21 |
5 |
|
T22 |
5 |
|
T23 |
5 |
| true |
3222 |
1 |
|
T1 |
8 |
|
T3 |
4 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10219 |
1 |
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
2 |
| others[1] |
796 |
1 |
|
T3 |
1 |
|
T19 |
14 |
|
T21 |
19 |
| others[2] |
792 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T18 |
1 |
| others[3] |
1247 |
1 |
|
T1 |
4 |
|
T3 |
1 |
|
T168 |
1 |
| false |
398 |
1 |
|
T3 |
1 |
|
T19 |
3 |
|
T21 |
11 |
| true |
532 |
1 |
|
T3 |
7 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10187 |
1 |
|
T2 |
2 |
|
T3 |
2 |
|
T5 |
174 |
| others[1] |
765 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T18 |
1 |
| others[2] |
792 |
1 |
|
T1 |
3 |
|
T19 |
9 |
|
T43 |
1 |
| others[3] |
1306 |
1 |
|
T1 |
2 |
|
T3 |
1 |
|
T17 |
1 |
| false |
380 |
1 |
|
T19 |
10 |
|
T21 |
11 |
|
T22 |
9 |
| true |
554 |
1 |
|
T3 |
9 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2393 |
1 |
|
T3 |
2 |
|
T5 |
40 |
|
T42 |
1 |
| others[1] |
2456 |
1 |
|
T3 |
3 |
|
T7 |
1 |
|
T5 |
26 |
| others[2] |
2356 |
1 |
|
T3 |
2 |
|
T5 |
27 |
|
T24 |
26 |
| others[3] |
3975 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T4 |
1 |
| false |
1305 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
17 |
| true |
1499 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9748 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
1 |
| others[1] |
246 |
1 |
|
T3 |
1 |
|
T21 |
14 |
|
T87 |
1 |
| others[2] |
262 |
1 |
|
T1 |
1 |
|
T3 |
4 |
|
T7 |
1 |
| others[3] |
479 |
1 |
|
T1 |
2 |
|
T3 |
1 |
|
T27 |
1 |
| false |
140 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T21 |
5 |
| true |
3109 |
1 |
|
T1 |
2 |
|
T3 |
4 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9891 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
| others[1] |
456 |
1 |
|
T3 |
3 |
|
T4 |
1 |
|
T6 |
1 |
| others[2] |
475 |
1 |
|
T1 |
1 |
|
T3 |
3 |
|
T7 |
1 |
| others[3] |
761 |
1 |
|
T1 |
2 |
|
T3 |
4 |
|
T17 |
1 |
| false |
226 |
1 |
|
T3 |
1 |
|
T18 |
1 |
|
T19 |
3 |
| true |
2175 |
1 |
|
T1 |
4 |
|
T7 |
3 |
|
T168 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9687 |
1 |
|
T2 |
2 |
|
T5 |
174 |
|
T168 |
1 |
| others[1] |
285 |
1 |
|
T3 |
2 |
|
T21 |
9 |
|
T22 |
17 |
| others[2] |
255 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
429 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T27 |
1 |
| false |
149 |
1 |
|
T7 |
1 |
|
T43 |
1 |
|
T21 |
2 |
| true |
3179 |
1 |
|
T1 |
8 |
|
T3 |
6 |
|
T7 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9709 |
1 |
|
T2 |
2 |
|
T7 |
2 |
|
T5 |
174 |
| others[1] |
244 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T168 |
1 |
| others[2] |
269 |
1 |
|
T3 |
3 |
|
T18 |
1 |
|
T21 |
13 |
| others[3] |
409 |
1 |
|
T3 |
3 |
|
T42 |
1 |
|
T21 |
6 |
| false |
131 |
1 |
|
T21 |
3 |
|
T22 |
9 |
|
T23 |
11 |
| true |
3222 |
1 |
|
T1 |
8 |
|
T3 |
5 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10253 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
2 |
| others[1] |
774 |
1 |
|
T1 |
3 |
|
T42 |
1 |
|
T19 |
12 |
| others[2] |
737 |
1 |
|
T3 |
4 |
|
T19 |
13 |
|
T43 |
1 |
| others[3] |
1289 |
1 |
|
T1 |
3 |
|
T3 |
1 |
|
T19 |
18 |
| false |
411 |
1 |
|
T1 |
1 |
|
T19 |
3 |
|
T21 |
9 |
| true |
520 |
1 |
|
T3 |
5 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10198 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
174 |
| others[1] |
764 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| others[2] |
764 |
1 |
|
T1 |
3 |
|
T3 |
2 |
|
T19 |
6 |
| others[3] |
1311 |
1 |
|
T1 |
3 |
|
T3 |
2 |
|
T18 |
1 |
| false |
405 |
1 |
|
T19 |
5 |
|
T21 |
10 |
|
T22 |
12 |
| true |
542 |
1 |
|
T3 |
7 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2423 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
45 |
| others[1] |
2320 |
1 |
|
T3 |
2 |
|
T5 |
35 |
|
T24 |
32 |
| others[2] |
2408 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
25 |
| others[3] |
4084 |
1 |
|
T3 |
8 |
|
T4 |
1 |
|
T5 |
55 |
| false |
1240 |
1 |
|
T7 |
1 |
|
T5 |
14 |
|
T24 |
15 |
| true |
1509 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9754 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
| others[1] |
265 |
1 |
|
T3 |
3 |
|
T18 |
1 |
|
T21 |
12 |
| others[2] |
267 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T42 |
1 |
| others[3] |
431 |
1 |
|
T3 |
4 |
|
T21 |
12 |
|
T101 |
1 |
| false |
158 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T21 |
6 |
| true |
3109 |
1 |
|
T1 |
6 |
|
T3 |
4 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9939 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T5 |
174 |
| others[1] |
433 |
1 |
|
T1 |
2 |
|
T7 |
2 |
|
T19 |
5 |
| others[2] |
467 |
1 |
|
T3 |
3 |
|
T7 |
1 |
|
T42 |
1 |
| others[3] |
726 |
1 |
|
T1 |
2 |
|
T3 |
9 |
|
T7 |
1 |
| false |
250 |
1 |
|
T19 |
5 |
|
T21 |
4 |
|
T22 |
5 |
| true |
2169 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9712 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
174 |
| others[1] |
246 |
1 |
|
T3 |
2 |
|
T7 |
2 |
|
T27 |
1 |
| others[2] |
262 |
1 |
|
T3 |
2 |
|
T17 |
1 |
|
T21 |
7 |
| others[3] |
448 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T168 |
1 |
| false |
148 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T43 |
1 |
| true |
3168 |
1 |
|
T1 |
8 |
|
T3 |
4 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9709 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T7 |
1 |
| others[1] |
230 |
1 |
|
T4 |
1 |
|
T21 |
7 |
|
T78 |
1 |
| others[2] |
256 |
1 |
|
T7 |
1 |
|
T21 |
12 |
|
T87 |
1 |
| others[3] |
385 |
1 |
|
T3 |
3 |
|
T18 |
1 |
|
T21 |
13 |
| false |
141 |
1 |
|
T21 |
6 |
|
T22 |
5 |
|
T23 |
9 |
| true |
3263 |
1 |
|
T1 |
8 |
|
T3 |
8 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10234 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
| others[1] |
772 |
1 |
|
T1 |
2 |
|
T3 |
1 |
|
T4 |
1 |
| others[2] |
765 |
1 |
|
T1 |
3 |
|
T7 |
1 |
|
T19 |
13 |
| others[3] |
1297 |
1 |
|
T1 |
2 |
|
T3 |
1 |
|
T6 |
1 |
| false |
390 |
1 |
|
T3 |
1 |
|
T168 |
1 |
|
T19 |
7 |
| true |
526 |
1 |
|
T3 |
8 |
|
T7 |
3 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10249 |
1 |
|
T2 |
2 |
|
T3 |
2 |
|
T5 |
174 |
| others[1] |
778 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
12 |
| others[2] |
730 |
1 |
|
T1 |
1 |
|
T18 |
1 |
|
T19 |
10 |
| others[3] |
1298 |
1 |
|
T1 |
6 |
|
T3 |
2 |
|
T168 |
1 |
| false |
381 |
1 |
|
T19 |
6 |
|
T21 |
7 |
|
T22 |
10 |
| true |
548 |
1 |
|
T3 |
8 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2490 |
1 |
|
T7 |
1 |
|
T5 |
32 |
|
T24 |
40 |
| others[1] |
2395 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
37 |
| others[2] |
2365 |
1 |
|
T3 |
4 |
|
T5 |
33 |
|
T42 |
1 |
| others[3] |
3965 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T5 |
54 |
| false |
1259 |
1 |
|
T3 |
2 |
|
T4 |
1 |
|
T5 |
18 |
| true |
1510 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9743 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
3 |
| others[1] |
266 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| others[2] |
248 |
1 |
|
T3 |
1 |
|
T21 |
7 |
|
T22 |
8 |
| others[3] |
447 |
1 |
|
T1 |
1 |
|
T3 |
3 |
|
T21 |
12 |
| false |
137 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T27 |
1 |
| true |
3143 |
1 |
|
T1 |
4 |
|
T3 |
3 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |