Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9920 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
2 |
| others[1] |
443 |
1 |
|
T3 |
2 |
|
T19 |
2 |
|
T21 |
6 |
| others[2] |
456 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T19 |
3 |
| others[3] |
767 |
1 |
|
T1 |
3 |
|
T3 |
6 |
|
T7 |
2 |
| false |
254 |
1 |
|
T42 |
1 |
|
T168 |
1 |
|
T27 |
1 |
| true |
2144 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9720 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T7 |
1 |
| others[1] |
263 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T21 |
6 |
| others[2] |
262 |
1 |
|
T7 |
1 |
|
T21 |
6 |
|
T22 |
5 |
| others[3] |
430 |
1 |
|
T3 |
3 |
|
T21 |
24 |
|
T101 |
1 |
| false |
133 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T17 |
1 |
| true |
3176 |
1 |
|
T1 |
8 |
|
T3 |
6 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9714 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T7 |
1 |
| others[1] |
275 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T17 |
1 |
| others[2] |
233 |
1 |
|
T3 |
2 |
|
T21 |
11 |
|
T78 |
1 |
| others[3] |
430 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T42 |
1 |
| false |
121 |
1 |
|
T3 |
1 |
|
T21 |
6 |
|
T22 |
7 |
| true |
3211 |
1 |
|
T1 |
8 |
|
T3 |
6 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10206 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T5 |
174 |
| others[1] |
764 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T6 |
1 |
| others[2] |
787 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
7 |
| others[3] |
1314 |
1 |
|
T1 |
2 |
|
T7 |
1 |
|
T19 |
18 |
| false |
396 |
1 |
|
T1 |
1 |
|
T3 |
3 |
|
T19 |
3 |
| true |
517 |
1 |
|
T3 |
7 |
|
T7 |
4 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10243 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
| others[1] |
781 |
1 |
|
T1 |
4 |
|
T19 |
14 |
|
T21 |
22 |
| others[2] |
769 |
1 |
|
T6 |
1 |
|
T19 |
7 |
|
T21 |
16 |
| others[3] |
1248 |
1 |
|
T1 |
3 |
|
T3 |
2 |
|
T4 |
1 |
| false |
389 |
1 |
|
T19 |
4 |
|
T21 |
8 |
|
T101 |
1 |
| true |
554 |
1 |
|
T3 |
9 |
|
T7 |
5 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2349 |
1 |
|
T7 |
1 |
|
T5 |
31 |
|
T24 |
37 |
| others[1] |
2486 |
1 |
|
T3 |
3 |
|
T5 |
35 |
|
T24 |
35 |
| others[2] |
2447 |
1 |
|
T3 |
2 |
|
T5 |
29 |
|
T17 |
1 |
| others[3] |
4037 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T4 |
1 |
| false |
1165 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T5 |
18 |
| true |
1500 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T7 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9724 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T7 |
1 |
| others[1] |
282 |
1 |
|
T3 |
1 |
|
T21 |
9 |
|
T22 |
7 |
| others[2] |
257 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T42 |
1 |
| others[3] |
418 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T18 |
1 |
| false |
131 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T101 |
1 |
| true |
3172 |
1 |
|
T1 |
4 |
|
T3 |
8 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9931 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
3 |
| others[1] |
457 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T19 |
5 |
| others[2] |
411 |
1 |
|
T1 |
2 |
|
T3 |
3 |
|
T7 |
1 |
| others[3] |
744 |
1 |
|
T1 |
1 |
|
T3 |
6 |
|
T42 |
1 |
| false |
222 |
1 |
|
T1 |
1 |
|
T19 |
2 |
|
T21 |
4 |
| true |
2219 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9706 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
174 |
| others[1] |
266 |
1 |
|
T7 |
1 |
|
T43 |
1 |
|
T21 |
14 |
| others[2] |
238 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T42 |
1 |
| others[3] |
438 |
1 |
|
T3 |
3 |
|
T6 |
1 |
|
T7 |
2 |
| false |
131 |
1 |
|
T3 |
1 |
|
T21 |
7 |
|
T22 |
6 |
| true |
3205 |
1 |
|
T1 |
8 |
|
T3 |
7 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9723 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
174 |
| others[1] |
239 |
1 |
|
T3 |
3 |
|
T21 |
9 |
|
T22 |
11 |
| others[2] |
270 |
1 |
|
T7 |
1 |
|
T21 |
9 |
|
T78 |
1 |
| others[3] |
378 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T43 |
1 |
| false |
126 |
1 |
|
T21 |
7 |
|
T22 |
6 |
|
T23 |
4 |
| true |
3248 |
1 |
|
T1 |
8 |
|
T3 |
7 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10214 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
174 |
| others[1] |
726 |
1 |
|
T1 |
2 |
|
T3 |
1 |
|
T19 |
15 |
| others[2] |
772 |
1 |
|
T1 |
1 |
|
T3 |
3 |
|
T168 |
1 |
| others[3] |
1355 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T18 |
1 |
| false |
405 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
3 |
| true |
512 |
1 |
|
T3 |
7 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10198 |
1 |
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
3 |
| others[1] |
758 |
1 |
|
T17 |
1 |
|
T19 |
8 |
|
T43 |
1 |
| others[2] |
790 |
1 |
|
T1 |
2 |
|
T3 |
3 |
|
T4 |
1 |
| others[3] |
1308 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T19 |
22 |
| false |
385 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
3 |
| true |
545 |
1 |
|
T3 |
3 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2442 |
1 |
|
T3 |
1 |
|
T5 |
47 |
|
T24 |
44 |
| others[1] |
2447 |
1 |
|
T3 |
2 |
|
T5 |
31 |
|
T17 |
1 |
| others[2] |
2416 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T5 |
30 |
| others[3] |
3960 |
1 |
|
T2 |
1 |
|
T3 |
3 |
|
T4 |
1 |
| false |
1243 |
1 |
|
T3 |
2 |
|
T5 |
13 |
|
T42 |
1 |
| true |
1476 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9760 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
2 |
| others[1] |
246 |
1 |
|
T6 |
1 |
|
T42 |
1 |
|
T21 |
9 |
| others[2] |
262 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T7 |
1 |
| others[3] |
441 |
1 |
|
T3 |
3 |
|
T21 |
19 |
|
T87 |
1 |
| false |
141 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T21 |
4 |
| true |
3134 |
1 |
|
T1 |
6 |
|
T3 |
5 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9943 |
1 |
|
T2 |
2 |
|
T3 |
5 |
|
T5 |
174 |
| others[1] |
469 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T19 |
9 |
| others[2] |
490 |
1 |
|
T3 |
3 |
|
T19 |
3 |
|
T21 |
14 |
| others[3] |
779 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
| false |
253 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T19 |
5 |
| true |
2050 |
1 |
|
T1 |
8 |
|
T7 |
3 |
|
T168 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9698 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T7 |
2 |
| others[1] |
257 |
1 |
|
T3 |
3 |
|
T21 |
8 |
|
T22 |
8 |
| others[2] |
229 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T43 |
1 |
| others[3] |
436 |
1 |
|
T3 |
2 |
|
T27 |
1 |
|
T21 |
13 |
| false |
149 |
1 |
|
T6 |
1 |
|
T7 |
1 |
|
T21 |
8 |
| true |
3215 |
1 |
|
T1 |
8 |
|
T3 |
4 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9704 |
1 |
|
T2 |
2 |
|
T3 |
2 |
|
T5 |
174 |
| others[1] |
253 |
1 |
|
T3 |
2 |
|
T21 |
9 |
|
T22 |
9 |
| others[2] |
219 |
1 |
|
T3 |
1 |
|
T42 |
1 |
|
T18 |
1 |
| others[3] |
389 |
1 |
|
T7 |
1 |
|
T21 |
21 |
|
T22 |
21 |
| false |
143 |
1 |
|
T3 |
1 |
|
T21 |
6 |
|
T22 |
3 |
| true |
3276 |
1 |
|
T1 |
8 |
|
T3 |
6 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10242 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
| others[1] |
742 |
1 |
|
T1 |
1 |
|
T168 |
1 |
|
T19 |
9 |
| others[2] |
768 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
8 |
| others[3] |
1315 |
1 |
|
T1 |
3 |
|
T3 |
2 |
|
T4 |
1 |
| false |
403 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T21 |
12 |
| true |
514 |
1 |
|
T3 |
7 |
|
T6 |
1 |
|
T7 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10286 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
3 |
| others[1] |
792 |
1 |
|
T1 |
1 |
|
T3 |
2 |
|
T6 |
1 |
| others[2] |
739 |
1 |
|
T1 |
2 |
|
T3 |
1 |
|
T168 |
1 |
| others[3] |
1246 |
1 |
|
T1 |
3 |
|
T3 |
2 |
|
T4 |
1 |
| false |
391 |
1 |
|
T19 |
5 |
|
T21 |
7 |
|
T22 |
9 |
| true |
530 |
1 |
|
T3 |
4 |
|
T7 |
5 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2399 |
1 |
|
T3 |
5 |
|
T7 |
1 |
|
T5 |
42 |
| others[1] |
2448 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| others[2] |
2397 |
1 |
|
T2 |
1 |
|
T3 |
2 |
|
T5 |
33 |
| others[3] |
4014 |
1 |
|
T3 |
3 |
|
T5 |
50 |
|
T42 |
1 |
| false |
1219 |
1 |
|
T3 |
1 |
|
T5 |
18 |
|
T24 |
19 |
| true |
1507 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T7 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9723 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
| others[1] |
267 |
1 |
|
T1 |
2 |
|
T3 |
2 |
|
T21 |
12 |
| others[2] |
267 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T21 |
9 |
| others[3] |
411 |
1 |
|
T3 |
2 |
|
T7 |
1 |
|
T21 |
17 |
| false |
128 |
1 |
|
T7 |
1 |
|
T42 |
1 |
|
T168 |
1 |
| true |
3188 |
1 |
|
T1 |
4 |
|
T3 |
6 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9951 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
| others[1] |
470 |
1 |
|
T3 |
5 |
|
T18 |
1 |
|
T19 |
5 |
| others[2] |
439 |
1 |
|
T3 |
1 |
|
T168 |
1 |
|
T19 |
7 |
| others[3] |
799 |
1 |
|
T3 |
3 |
|
T4 |
1 |
|
T7 |
1 |
| false |
233 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T21 |
9 |
| true |
2092 |
1 |
|
T1 |
6 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9733 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T7 |
2 |
| others[1] |
264 |
1 |
|
T3 |
2 |
|
T168 |
1 |
|
T21 |
8 |
| others[2] |
241 |
1 |
|
T21 |
14 |
|
T101 |
1 |
|
T22 |
7 |
| others[3] |
409 |
1 |
|
T3 |
4 |
|
T6 |
1 |
|
T7 |
1 |
| false |
138 |
1 |
|
T21 |
9 |
|
T22 |
4 |
|
T23 |
4 |
| true |
3199 |
1 |
|
T1 |
8 |
|
T3 |
5 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9739 |
1 |
|
T2 |
2 |
|
T7 |
2 |
|
T5 |
174 |
| others[1] |
229 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T21 |
10 |
| others[2] |
247 |
1 |
|
T7 |
2 |
|
T21 |
4 |
|
T22 |
8 |
| others[3] |
383 |
1 |
|
T3 |
2 |
|
T168 |
1 |
|
T21 |
18 |
| false |
136 |
1 |
|
T3 |
4 |
|
T21 |
1 |
|
T22 |
2 |
| true |
3250 |
1 |
|
T1 |
8 |
|
T3 |
5 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10254 |
1 |
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
1 |
| others[1] |
753 |
1 |
|
T1 |
1 |
|
T19 |
8 |
|
T21 |
17 |
| others[2] |
824 |
1 |
|
T1 |
2 |
|
T19 |
8 |
|
T21 |
19 |
| others[3] |
1208 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T168 |
1 |
| false |
408 |
1 |
|
T1 |
1 |
|
T3 |
2 |
|
T27 |
1 |
| true |
537 |
1 |
|
T3 |
8 |
|
T6 |
1 |
|
T7 |
5 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |