Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	225660	1		T1	4		T2	1		T3	15
auto[FlashEraseBank]	250376	1		T1	4		T3	18		T4	540

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	265960	1		T1	4		T2	1		T3	15
auto[FlashOpProgram]	190291	1		T1	4		T3	17		T4	1088
auto[FlashOpErase]	15785	1		T3	1		T5	256		T32	6
auto[FlashOpInvalid]	4000	1		T185	200		T107	200		T279	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	265960	1		T1	4		T2	1		T3	15
op[FlashOpProgram]	190291	1		T1	4		T3	17		T4	1088
op[FlashOpErase]	15785	1		T3	1		T5	256		T32	6
read_erase_read	845	1		T32	2		T33	2		T21	6
read_prog_read	1221	1		T1	3		T3	3		T43	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	337921	1		T1	8		T2	1		T3	33
auto[FlashPartInfo]	134479	1		T4	269		T6	249		T7	20
auto[FlashPartInfo1]	897	1		T18	9		T43	2		T53	4
auto[FlashPartInfo2]	2739	1		T7	1		T27	3		T18	17

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	203405	1		T1	4		T2	1		T3	15
auto[FlashPartData]	auto[FlashOpProgram]	127004	1		T1	4		T3	17		T4	819
auto[FlashPartData]	auto[FlashOpErase]	3584	1		T3	1		T12	1		T21	31
auto[FlashPartData]	auto[FlashOpInvalid]	3928	1		T185	198		T107	198		T279	194
auto[FlashPartInfo]	auto[FlashOpRead]	60193	1		T6	249		T7	10		T5	524
auto[FlashPartInfo]	auto[FlashOpProgram]	62046	1		T4	269		T7	10		T5	256
auto[FlashPartInfo]	auto[FlashOpErase]	12182	1		T5	256		T32	6		T24	273
auto[FlashPartInfo]	auto[FlashOpInvalid]	58	1		T185	2		T107	2		T279	6
auto[FlashPartInfo1]	auto[FlashOpRead]	730	1		T18	9		T43	2		T53	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T95	1		T111	1		T381	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T73	1		T111	1		T382	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T111	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1632	1		T7	1		T27	3		T18	13
auto[FlashPartInfo2]	auto[FlashOpProgram]	1079	1		T18	4		T43	11		T72	1
auto[FlashPartInfo2]	auto[FlashOpErase]	16	1		T22	1		T383	1		T116	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T383	2		T117	2		T384	2