Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	7	25	78.12

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	7	25	78.12	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30571	1		T1	16		T5	488		T32	4
auto[1]	13	1		T316	1		T317	2		T318	1
auto[2]	104	1		T319	24		T320	3		T321	1
auto[3]	380	1		T27	1		T184	102		T40	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7803	1		T1	4		T5	122		T32	1
evic_idx[1]	7773	1		T1	4		T5	122		T32	1
evic_idx[2]	7751	1		T1	4		T5	122		T32	1
evic_idx[3]	7741	1		T1	4		T5	122		T32	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30064	1		T5	488		T24	552		T33	4
evic_op[2]	400	1		T1	16		T32	4		T27	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	7	25	78.12	7

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	4
[evic_idx[2]]	[evic_op[1]]	[auto[2]]	0	1	1
[evic_idx[3]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7437	1		T5	122		T24	138		T33	1
evic_idx[0]	evic_op[1]	auto[3]	116	1		T184	39		T322	9		T323	10
evic_idx[0]	evic_op[2]	auto[0]	60	1		T1	4		T32	1		T34	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T317	1		T324	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	24	1		T319	4		T192	1		T325	2
evic_idx[0]	evic_op[2]	auto[3]	13	1		T41	1		T175	1		T190	1
evic_idx[1]	evic_op[1]	auto[0]	7432	1		T5	122		T24	138		T33	1
evic_idx[1]	evic_op[1]	auto[3]	94	1		T184	29		T322	12		T323	5
evic_idx[1]	evic_op[2]	auto[0]	62	1		T1	4		T32	1		T34	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T324	1		T326	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	22	1		T319	7		T320	2		T192	1
evic_idx[1]	evic_op[2]	auto[3]	10	1		T177	1		T194	1		T190	1
evic_idx[2]	evic_op[1]	auto[0]	7431	1		T5	122		T24	138		T33	1
evic_idx[2]	evic_op[1]	auto[1]	1	1		T318	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	67	1		T184	17		T322	8		T323	4
evic_idx[2]	evic_op[2]	auto[0]	63	1		T1	4		T32	1		T34	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T316	1		T264	1		T327	1
evic_idx[2]	evic_op[2]	auto[2]	25	1		T319	9		T320	1		T192	1
evic_idx[2]	evic_op[2]	auto[3]	8	1		T27	1		T190	1		T328	1
evic_idx[3]	evic_op[1]	auto[0]	7428	1		T5	122		T24	138		T33	1
evic_idx[3]	evic_op[1]	auto[3]	58	1		T184	17		T322	5		T323	4
evic_idx[3]	evic_op[2]	auto[0]	66	1		T1	4		T32	1		T34	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T317	1		T264	1		T324	1
evic_idx[3]	evic_op[2]	auto[2]	21	1		T319	4		T321	1		T329	1
evic_idx[3]	evic_op[2]	auto[3]	14	1		T40	1		T41	1		T328	1