Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	23690	1		T37	2975		T187	2446		T330	8914
rd_lvl[2]	40970	1		T37	1914		T187	1660		T330	4958
rd_lvl[3]	9831	1		T37	705		T187	636		T331	1252
rd_lvl[4]	25056	1		T37	1016		T187	1022		T331	3640
rd_lvl[5]	21145	1		T37	956		T187	790		T331	492
rd_lvl[6]	17598	1		T20	919		T37	6		T213	1094
rd_lvl[7]	13972	1		T20	723		T37	931		T213	956
rd_lvl[8]	11995	1		T37	930		T217	1247		T187	776
rd_lvl[9]	7323	1		T37	1462		T35	371		T217	225
rd_lvl[10]	5920	1		T37	398		T35	605		T187	310
rd_lvl[11]	5738	1		T187	220		T268	569		T201	847
rd_lvl[12]	5004	1		T35	4		T214	720		T187	2
rd_lvl[13]	3628	1		T214	332		T187	1		T268	36
rd_lvl[14]	7372	1		T36	608		T62	548		T187	58
rd_lvl[15]	4268	1		T6	198		T36	355		T62	352