Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	314073	1		T1	2		T2	1		T3	22
all_pins[1]	314073	1		T1	2		T2	1		T3	22
all_pins[2]	314073	1		T1	2		T2	1		T3	22
all_pins[3]	314073	1		T1	2		T2	1		T3	22
all_pins[4]	314073	1		T1	2		T2	1		T3	22
all_pins[5]	314073	1		T1	2		T2	1		T3	22

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1575410	1		T1	12		T2	6		T3	132
values[0x1]	309028	1		T4	1088		T6	3390		T20	2463
transitions[0x0=>0x1]	285897	1		T4	1088		T6	2350		T20	2463
transitions[0x1=>0x0]	285882	1		T4	1088		T6	2350		T20	2463

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	313923	1		T1	2		T2	1		T3	22
all_pins[0]	values[0x1]	150	1		T244	1		T245	5		T246	1
all_pins[0]	transitions[0x0=>0x1]	82	1		T244	1		T310	1		T311	2
all_pins[0]	transitions[0x1=>0x0]	94	1		T246	1		T310	2		T311	1
all_pins[1]	values[0x0]	313911	1		T1	2		T2	1		T3	22
all_pins[1]	values[0x1]	162	1		T245	5		T246	2		T310	6
all_pins[1]	transitions[0x0=>0x1]	137	1		T245	5		T246	1		T310	6
all_pins[1]	transitions[0x1=>0x0]	1275	1		T6	520		T36	65		T336	17
all_pins[2]	values[0x0]	312773	1		T1	2		T2	1		T3	22
all_pins[2]	values[0x1]	1300	1		T6	520		T36	65		T336	17
all_pins[2]	transitions[0x0=>0x1]	43	1		T245	3		T246	1		T311	1
all_pins[2]	transitions[0x1=>0x0]	204144	1		T6	672		T20	1642		T37	11293
all_pins[3]	values[0x0]	108672	1		T1	2		T2	1		T3	22
all_pins[3]	values[0x1]	205401	1		T6	1192		T20	1642		T37	11293
all_pins[3]	transitions[0x0=>0x1]	183669	1		T6	672		T20	1642		T37	10089
all_pins[3]	transitions[0x1=>0x0]	80217	1		T4	1088		T6	1158		T20	821
all_pins[4]	values[0x0]	212124	1		T1	2		T2	1		T3	22
all_pins[4]	values[0x1]	101949	1		T4	1088		T6	1678		T20	821
all_pins[4]	transitions[0x0=>0x1]	101937	1		T4	1088		T6	1678		T20	821
all_pins[4]	transitions[0x1=>0x0]	54	1		T245	3		T246	2		T310	1
all_pins[5]	values[0x0]	314007	1		T1	2		T2	1		T3	22
all_pins[5]	values[0x1]	66	1		T245	4		T246	2		T310	2
all_pins[5]	transitions[0x0=>0x1]	29	1		T245	2		T246	2		T311	2
all_pins[5]	transitions[0x1=>0x0]	98	1		T244	1		T245	3		T246	1