Unified Coverage Report :: Group :: tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::phy_rd_cg

Group : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::phy_rd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

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Summary for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::phy_rd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if::phy_rd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
read_pat	3	0	3	100.00	100	1	1	0

Summary for Variable read_pat

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for read_pat

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
any2read[READ=>READ]	6430807	1		T1	51		T2	98304		T3	60
any2read[PROG=>READ]	1087961	1		T1	2		T2	32768		T3	1
any2read[ERASE=>READ]	1450	1		T3	1		T21	1		T22	3