Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T244	4		T245	7		T246	7
all_values[1]	284	1		T244	4		T245	7		T246	7
all_values[2]	284	1		T244	4		T245	7		T246	7
all_values[3]	284	1		T244	4		T245	7		T246	7
all_values[4]	284	1		T244	4		T245	7		T246	7
all_values[5]	284	1		T244	4		T245	7		T246	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	937	1		T244	16		T245	22		T246	28
auto[1]	767	1		T244	8		T245	20		T246	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	552	1		T244	12		T245	13		T246	12
auto[1]	1152	1		T244	12		T245	29		T246	30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1009	1		T244	20		T245	28		T246	25
auto[1]	695	1		T244	4		T245	14		T246	17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	105	1		T244	3		T245	4		T246	3
all_values[0]	auto[0]	auto[1]	auto[1]	66	1		T244	1		T245	3		T246	1
all_values[0]	auto[1]	auto[0]	auto[1]	61	1		T246	3		T310	1		T311	3
all_values[0]	auto[1]	auto[1]	auto[1]	52	1		T310	2		T311	2		T312	1
all_values[1]	auto[0]	auto[0]	auto[1]	91	1		T244	3		T245	1		T246	4
all_values[1]	auto[0]	auto[1]	auto[1]	77	1		T245	2		T246	1		T310	4
all_values[1]	auto[1]	auto[0]	auto[1]	64	1		T244	1		T245	3		T246	2
all_values[1]	auto[1]	auto[1]	auto[1]	52	1		T245	1		T310	1		T311	2
all_values[2]	auto[0]	auto[0]	auto[0]	98	1		T244	2		T245	3		T310	1
all_values[2]	auto[0]	auto[1]	auto[0]	67	1		T244	2		T245	1		T246	4
all_values[2]	auto[1]	auto[0]	auto[1]	56	1		T310	4		T311	1		T313	1
all_values[2]	auto[1]	auto[1]	auto[1]	63	1		T245	3		T246	3		T310	1
all_values[3]	auto[0]	auto[0]	auto[0]	103	1		T244	2		T245	6		T246	4
all_values[3]	auto[0]	auto[1]	auto[0]	68	1		T310	2		T311	2		T312	1
all_values[3]	auto[1]	auto[0]	auto[1]	67	1		T244	1		T245	1		T246	2
all_values[3]	auto[1]	auto[1]	auto[1]	46	1		T244	1		T246	1		T310	2
all_values[4]	auto[0]	auto[0]	auto[0]	60	1		T244	2		T245	2		T246	3
all_values[4]	auto[0]	auto[0]	auto[1]	29	1		T244	1		T245	1		T310	2
all_values[4]	auto[0]	auto[1]	auto[0]	50	1		T245	1		T246	1		T310	1
all_values[4]	auto[0]	auto[1]	auto[1]	32	1		T311	2		T312	1		T314	2
all_values[4]	auto[1]	auto[0]	auto[1]	56	1		T246	2		T310	2		T311	4
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T244	1		T245	3		T246	1
all_values[5]	auto[0]	auto[0]	auto[0]	54	1		T244	1		T310	4		T311	2
all_values[5]	auto[0]	auto[0]	auto[1]	29	1		T246	3		T314	1		T315	2
all_values[5]	auto[0]	auto[1]	auto[0]	52	1		T244	3		T312	1		T313	1
all_values[5]	auto[0]	auto[1]	auto[1]	28	1		T245	4		T246	1		T310	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T245	1		T246	2		T310	1
all_values[5]	auto[1]	auto[1]	auto[1]	57	1		T245	2		T246	1		T310	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal