| T1077 |
/workspace/coverage/default/1.flash_ctrl_smoke_hw.1890876351 |
|
|
Mar 12 01:21:28 PM PDT 24 |
Mar 12 01:21:52 PM PDT 24 |
38451700 ps |
| T1078 |
/workspace/coverage/default/4.flash_ctrl_intr_rd.1432297769 |
|
|
Mar 12 01:24:30 PM PDT 24 |
Mar 12 01:27:13 PM PDT 24 |
2225735200 ps |
| T1079 |
/workspace/coverage/default/38.flash_ctrl_rw_evict.3545130150 |
|
|
Mar 12 01:33:47 PM PDT 24 |
Mar 12 01:34:20 PM PDT 24 |
66740800 ps |
| T1080 |
/workspace/coverage/default/26.flash_ctrl_smoke.1090892317 |
|
|
Mar 12 01:32:07 PM PDT 24 |
Mar 12 01:34:13 PM PDT 24 |
29769800 ps |
| T1081 |
/workspace/coverage/default/16.flash_ctrl_otp_reset.483970040 |
|
|
Mar 12 01:29:52 PM PDT 24 |
Mar 12 01:31:45 PM PDT 24 |
144188700 ps |
| T1082 |
/workspace/coverage/default/30.flash_ctrl_sec_info_access.1103688030 |
|
|
Mar 12 01:32:46 PM PDT 24 |
Mar 12 01:34:07 PM PDT 24 |
2597125200 ps |
| T1083 |
/workspace/coverage/default/24.flash_ctrl_rw_evict.1805099378 |
|
|
Mar 12 01:31:53 PM PDT 24 |
Mar 12 01:32:27 PM PDT 24 |
93440100 ps |
| T1084 |
/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3446749084 |
|
|
Mar 12 01:32:34 PM PDT 24 |
Mar 12 01:33:05 PM PDT 24 |
32891900 ps |
| T1085 |
/workspace/coverage/default/16.flash_ctrl_rw_evict.972932260 |
|
|
Mar 12 01:29:50 PM PDT 24 |
Mar 12 01:30:21 PM PDT 24 |
42017400 ps |
| T1086 |
/workspace/coverage/default/16.flash_ctrl_disable.2516293706 |
|
|
Mar 12 01:29:49 PM PDT 24 |
Mar 12 01:30:12 PM PDT 24 |
10191200 ps |
| T1087 |
/workspace/coverage/default/0.flash_ctrl_serr_counter.1965919172 |
|
|
Mar 12 01:20:49 PM PDT 24 |
Mar 12 01:22:10 PM PDT 24 |
759591800 ps |
| T1088 |
/workspace/coverage/default/5.flash_ctrl_prog_reset.2956531306 |
|
|
Mar 12 01:25:07 PM PDT 24 |
Mar 12 01:25:21 PM PDT 24 |
35558200 ps |
| T1089 |
/workspace/coverage/default/66.flash_ctrl_otp_reset.406955423 |
|
|
Mar 12 01:34:53 PM PDT 24 |
Mar 12 01:37:12 PM PDT 24 |
135377000 ps |
| T1090 |
/workspace/coverage/default/5.flash_ctrl_error_prog_win.3554174915 |
|
|
Mar 12 01:24:56 PM PDT 24 |
Mar 12 01:37:59 PM PDT 24 |
432596600 ps |
| T1091 |
/workspace/coverage/default/5.flash_ctrl_rw.2116363013 |
|
|
Mar 12 01:25:09 PM PDT 24 |
Mar 12 01:33:53 PM PDT 24 |
6261459500 ps |
| T1092 |
/workspace/coverage/default/71.flash_ctrl_otp_reset.3517572856 |
|
|
Mar 12 01:35:08 PM PDT 24 |
Mar 12 01:37:01 PM PDT 24 |
150112800 ps |
| T1093 |
/workspace/coverage/default/6.flash_ctrl_mp_regions.1862963453 |
|
|
Mar 12 01:25:26 PM PDT 24 |
Mar 12 01:30:10 PM PDT 24 |
40725429200 ps |
| T1094 |
/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.4025530651 |
|
|
Mar 12 01:25:37 PM PDT 24 |
Mar 12 01:33:06 PM PDT 24 |
111216517600 ps |
| T1095 |
/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.147172269 |
|
|
Mar 12 01:22:04 PM PDT 24 |
Mar 12 01:22:36 PM PDT 24 |
34329700 ps |
| T1096 |
/workspace/coverage/default/0.flash_ctrl_error_prog_win.2263204202 |
|
|
Mar 12 01:20:38 PM PDT 24 |
Mar 12 01:35:15 PM PDT 24 |
1416548000 ps |
| T1097 |
/workspace/coverage/default/2.flash_ctrl_error_prog_type.2934944652 |
|
|
Mar 12 01:22:38 PM PDT 24 |
Mar 12 02:08:13 PM PDT 24 |
2048161500 ps |
| T1098 |
/workspace/coverage/default/39.flash_ctrl_sec_info_access.2706373888 |
|
|
Mar 12 01:33:57 PM PDT 24 |
Mar 12 01:35:02 PM PDT 24 |
4073452900 ps |
| T1099 |
/workspace/coverage/default/20.flash_ctrl_smoke.3770671471 |
|
|
Mar 12 01:30:55 PM PDT 24 |
Mar 12 01:33:50 PM PDT 24 |
77204500 ps |
| T1100 |
/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3376215506 |
|
|
Mar 12 01:23:18 PM PDT 24 |
Mar 12 01:24:58 PM PDT 24 |
337723000 ps |
| T1101 |
/workspace/coverage/default/9.flash_ctrl_connect.2861331054 |
|
|
Mar 12 01:27:13 PM PDT 24 |
Mar 12 01:27:29 PM PDT 24 |
41129500 ps |
| T1102 |
/workspace/coverage/default/32.flash_ctrl_disable.1311463769 |
|
|
Mar 12 01:32:59 PM PDT 24 |
Mar 12 01:33:20 PM PDT 24 |
44361100 ps |
| T1103 |
/workspace/coverage/default/6.flash_ctrl_rw.1603385401 |
|
|
Mar 12 01:25:28 PM PDT 24 |
Mar 12 01:34:28 PM PDT 24 |
5009592800 ps |
| T1104 |
/workspace/coverage/default/1.flash_ctrl_rw_derr.46272102 |
|
|
Mar 12 01:22:03 PM PDT 24 |
Mar 12 01:31:05 PM PDT 24 |
3256253600 ps |
| T1105 |
/workspace/coverage/default/39.flash_ctrl_rw_evict.4166793126 |
|
|
Mar 12 01:33:46 PM PDT 24 |
Mar 12 01:34:19 PM PDT 24 |
169740400 ps |
| T1106 |
/workspace/coverage/default/18.flash_ctrl_smoke.1702707946 |
|
|
Mar 12 01:30:24 PM PDT 24 |
Mar 12 01:31:16 PM PDT 24 |
51929000 ps |
| T1107 |
/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2777168984 |
|
|
Mar 12 01:28:03 PM PDT 24 |
Mar 12 01:28:17 PM PDT 24 |
15902800 ps |
| T1108 |
/workspace/coverage/default/27.flash_ctrl_alert_test.1851275679 |
|
|
Mar 12 01:32:24 PM PDT 24 |
Mar 12 01:32:38 PM PDT 24 |
53941000 ps |
| T1109 |
/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2090700430 |
|
|
Mar 12 01:30:24 PM PDT 24 |
Mar 12 01:30:38 PM PDT 24 |
25295900 ps |
| T1110 |
/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1431885207 |
|
|
Mar 12 01:27:38 PM PDT 24 |
Mar 12 01:30:14 PM PDT 24 |
10012366100 ps |
| T1111 |
/workspace/coverage/default/2.flash_ctrl_full_mem_access.1488586591 |
|
|
Mar 12 01:22:30 PM PDT 24 |
Mar 12 01:59:27 PM PDT 24 |
458233659900 ps |
| T1112 |
/workspace/coverage/default/25.flash_ctrl_otp_reset.4313852 |
|
|
Mar 12 01:31:52 PM PDT 24 |
Mar 12 01:34:11 PM PDT 24 |
107883100 ps |
| T1113 |
/workspace/coverage/default/8.flash_ctrl_alert_test.210881302 |
|
|
Mar 12 01:26:40 PM PDT 24 |
Mar 12 01:26:54 PM PDT 24 |
66665700 ps |
| T1114 |
/workspace/coverage/default/4.flash_ctrl_rand_ops.1300327477 |
|
|
Mar 12 01:24:03 PM PDT 24 |
Mar 12 01:29:44 PM PDT 24 |
147216500 ps |
| T1115 |
/workspace/coverage/default/27.flash_ctrl_prog_reset.1457794959 |
|
|
Mar 12 01:32:25 PM PDT 24 |
Mar 12 01:32:40 PM PDT 24 |
67584200 ps |
| T1116 |
/workspace/coverage/default/45.flash_ctrl_alert_test.3856477715 |
|
|
Mar 12 01:34:24 PM PDT 24 |
Mar 12 01:34:38 PM PDT 24 |
31029000 ps |
| T1117 |
/workspace/coverage/default/7.flash_ctrl_error_prog_win.1541381996 |
|
|
Mar 12 01:26:01 PM PDT 24 |
Mar 12 01:41:00 PM PDT 24 |
1428828900 ps |
| T1118 |
/workspace/coverage/default/4.flash_ctrl_host_dir_rd.106241143 |
|
|
Mar 12 01:24:15 PM PDT 24 |
Mar 12 01:25:23 PM PDT 24 |
39703000 ps |
| T1119 |
/workspace/coverage/default/13.flash_ctrl_ro.1779579817 |
|
|
Mar 12 01:28:45 PM PDT 24 |
Mar 12 01:30:34 PM PDT 24 |
1347817000 ps |
| T1120 |
/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.3273945241 |
|
|
Mar 12 01:31:15 PM PDT 24 |
Mar 12 01:33:17 PM PDT 24 |
1434372300 ps |
| T1121 |
/workspace/coverage/default/10.flash_ctrl_rand_ops.3817987198 |
|
|
Mar 12 01:27:18 PM PDT 24 |
Mar 12 01:42:27 PM PDT 24 |
524126900 ps |
| T1122 |
/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.4249633690 |
|
|
Mar 12 01:28:26 PM PDT 24 |
Mar 12 01:28:40 PM PDT 24 |
15114200 ps |
| T1123 |
/workspace/coverage/default/78.flash_ctrl_connect.1312104327 |
|
|
Mar 12 01:35:00 PM PDT 24 |
Mar 12 01:35:15 PM PDT 24 |
37950500 ps |
| T178 |
/workspace/coverage/default/2.flash_ctrl_rw_derr.47167384 |
|
|
Mar 12 01:22:58 PM PDT 24 |
Mar 12 01:34:29 PM PDT 24 |
16478025900 ps |
| T1124 |
/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2071948442 |
|
|
Mar 12 01:34:05 PM PDT 24 |
Mar 12 01:36:05 PM PDT 24 |
8142994400 ps |
| T1125 |
/workspace/coverage/default/43.flash_ctrl_otp_reset.3535342872 |
|
|
Mar 12 01:34:05 PM PDT 24 |
Mar 12 01:36:21 PM PDT 24 |
39310600 ps |
| T1126 |
/workspace/coverage/default/0.flash_ctrl_rw_derr.4225282739 |
|
|
Mar 12 01:20:51 PM PDT 24 |
Mar 12 01:30:20 PM PDT 24 |
2710142900 ps |
| T1127 |
/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.2262860507 |
|
|
Mar 12 01:32:24 PM PDT 24 |
Mar 12 01:34:43 PM PDT 24 |
1927054200 ps |
| T1128 |
/workspace/coverage/default/3.flash_ctrl_ro_serr.3322353396 |
|
|
Mar 12 01:23:41 PM PDT 24 |
Mar 12 01:26:10 PM PDT 24 |
1359580300 ps |
| T1129 |
/workspace/coverage/default/5.flash_ctrl_intr_rd.915983207 |
|
|
Mar 12 01:25:09 PM PDT 24 |
Mar 12 01:28:15 PM PDT 24 |
3266081300 ps |
| T1130 |
/workspace/coverage/default/47.flash_ctrl_connect.820990533 |
|
|
Mar 12 01:34:34 PM PDT 24 |
Mar 12 01:34:50 PM PDT 24 |
42560400 ps |
| T1131 |
/workspace/coverage/default/4.flash_ctrl_rw.1128219295 |
|
|
Mar 12 01:24:21 PM PDT 24 |
Mar 12 01:34:08 PM PDT 24 |
3870859400 ps |
| T1132 |
/workspace/coverage/default/11.flash_ctrl_phy_arb.1737714707 |
|
|
Mar 12 01:27:45 PM PDT 24 |
Mar 12 01:31:04 PM PDT 24 |
201867100 ps |
| T1133 |
/workspace/coverage/default/8.flash_ctrl_disable.1901169565 |
|
|
Mar 12 01:26:40 PM PDT 24 |
Mar 12 01:27:01 PM PDT 24 |
27319900 ps |
| T1134 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.456673061 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:06:44 PM PDT 24 |
248642400 ps |
| T59 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1300916905 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:13:48 PM PDT 24 |
180658500 ps |
| T1135 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.863834937 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:50 PM PDT 24 |
46260100 ps |
| T1136 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.286288349 |
|
|
Mar 12 01:06:20 PM PDT 24 |
Mar 12 01:06:36 PM PDT 24 |
39119600 ps |
| T244 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.385538177 |
|
|
Mar 12 01:06:46 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
53595800 ps |
| T60 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.4230524930 |
|
|
Mar 12 01:06:47 PM PDT 24 |
Mar 12 01:07:05 PM PDT 24 |
45974700 ps |
| T245 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2752808260 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:52 PM PDT 24 |
18868000 ps |
| T1137 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3684866076 |
|
|
Mar 12 01:06:11 PM PDT 24 |
Mar 12 01:06:24 PM PDT 24 |
21878300 ps |
| T1138 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3575986205 |
|
|
Mar 12 01:06:20 PM PDT 24 |
Mar 12 01:06:34 PM PDT 24 |
21384000 ps |
| T61 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2050963654 |
|
|
Mar 12 01:06:26 PM PDT 24 |
Mar 12 01:06:44 PM PDT 24 |
265045300 ps |
| T236 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3567981256 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:06:34 PM PDT 24 |
26721600 ps |
| T171 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1006974960 |
|
|
Mar 12 01:06:35 PM PDT 24 |
Mar 12 01:06:52 PM PDT 24 |
113745800 ps |
| T246 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1378244140 |
|
|
Mar 12 01:06:38 PM PDT 24 |
Mar 12 01:06:52 PM PDT 24 |
47780500 ps |
| T237 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3789655304 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:06:48 PM PDT 24 |
113880500 ps |
| T310 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.139026988 |
|
|
Mar 12 01:06:41 PM PDT 24 |
Mar 12 01:06:55 PM PDT 24 |
16659300 ps |
| T311 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1479885896 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:32 PM PDT 24 |
78423800 ps |
| T202 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1743319048 |
|
|
Mar 12 01:06:42 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
40809100 ps |
| T205 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3172946236 |
|
|
Mar 12 01:06:10 PM PDT 24 |
Mar 12 01:07:49 PM PDT 24 |
18267676400 ps |
| T312 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.942675045 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:53 PM PDT 24 |
44853100 ps |
| T242 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1520784242 |
|
|
Mar 12 01:06:05 PM PDT 24 |
Mar 12 01:06:44 PM PDT 24 |
1214729700 ps |
| T238 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2898428940 |
|
|
Mar 12 01:06:34 PM PDT 24 |
Mar 12 01:06:49 PM PDT 24 |
60133300 ps |
| T203 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2090351813 |
|
|
Mar 12 01:06:38 PM PDT 24 |
Mar 12 01:21:35 PM PDT 24 |
344929500 ps |
| T1139 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.811516615 |
|
|
Mar 12 01:06:29 PM PDT 24 |
Mar 12 01:06:43 PM PDT 24 |
12909400 ps |
| T1140 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4206050665 |
|
|
Mar 12 01:06:32 PM PDT 24 |
Mar 12 01:06:50 PM PDT 24 |
327989700 ps |
| T284 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1066483010 |
|
|
Mar 12 01:06:24 PM PDT 24 |
Mar 12 01:06:42 PM PDT 24 |
137576600 ps |
| T314 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2714743001 |
|
|
Mar 12 01:06:42 PM PDT 24 |
Mar 12 01:06:56 PM PDT 24 |
18370100 ps |
| T204 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4277200793 |
|
|
Mar 12 01:06:40 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
119656800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.686666687 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:34 PM PDT 24 |
154461300 ps |
| T348 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2176677533 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:06:48 PM PDT 24 |
28526700 ps |
| T206 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1817024543 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:21:22 PM PDT 24 |
1481747500 ps |
| T1142 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3986641146 |
|
|
Mar 12 01:06:10 PM PDT 24 |
Mar 12 01:06:24 PM PDT 24 |
51414400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.318883052 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:34 PM PDT 24 |
14160700 ps |
| T1144 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1645825907 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:33 PM PDT 24 |
191329100 ps |
| T313 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1102006008 |
|
|
Mar 12 01:06:35 PM PDT 24 |
Mar 12 01:06:49 PM PDT 24 |
16820800 ps |
| T1145 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1171355879 |
|
|
Mar 12 01:06:10 PM PDT 24 |
Mar 12 01:06:24 PM PDT 24 |
26049500 ps |
| T1146 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3269633267 |
|
|
Mar 12 01:06:44 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
80624900 ps |
| T218 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1280458770 |
|
|
Mar 12 01:06:12 PM PDT 24 |
Mar 12 01:06:31 PM PDT 24 |
122795000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1529511189 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:36 PM PDT 24 |
115684600 ps |
| T219 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.765169229 |
|
|
Mar 12 01:06:11 PM PDT 24 |
Mar 12 01:06:27 PM PDT 24 |
33366900 ps |
| T292 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.998207388 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:06:33 PM PDT 24 |
150815300 ps |
| T1148 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3425479161 |
|
|
Mar 12 01:06:38 PM PDT 24 |
Mar 12 01:06:54 PM PDT 24 |
11456800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1427577064 |
|
|
Mar 12 01:06:47 PM PDT 24 |
Mar 12 01:07:01 PM PDT 24 |
16503400 ps |
| T1150 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.197990064 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:51 PM PDT 24 |
36925500 ps |
| T220 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2764826525 |
|
|
Mar 12 01:06:32 PM PDT 24 |
Mar 12 01:06:49 PM PDT 24 |
40383600 ps |
| T1151 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4069444023 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:33 PM PDT 24 |
16919900 ps |
| T1152 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2439176113 |
|
|
Mar 12 01:06:05 PM PDT 24 |
Mar 12 01:06:36 PM PDT 24 |
92166000 ps |
| T221 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3997810651 |
|
|
Mar 12 01:06:47 PM PDT 24 |
Mar 12 01:07:08 PM PDT 24 |
72615400 ps |
| T1153 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.257820535 |
|
|
Mar 12 01:06:35 PM PDT 24 |
Mar 12 01:06:49 PM PDT 24 |
55587900 ps |
| T1154 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.966613942 |
|
|
Mar 12 01:06:28 PM PDT 24 |
Mar 12 01:06:44 PM PDT 24 |
16902700 ps |
| T1155 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3285818630 |
|
|
Mar 12 01:06:13 PM PDT 24 |
Mar 12 01:06:26 PM PDT 24 |
20514500 ps |
| T222 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2182183353 |
|
|
Mar 12 01:06:11 PM PDT 24 |
Mar 12 01:06:30 PM PDT 24 |
61529400 ps |
| T315 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3499723487 |
|
|
Mar 12 01:06:43 PM PDT 24 |
Mar 12 01:06:57 PM PDT 24 |
18018000 ps |
| T249 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1730390825 |
|
|
Mar 12 01:06:13 PM PDT 24 |
Mar 12 01:20:56 PM PDT 24 |
928436700 ps |
| T1156 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1666601194 |
|
|
Mar 12 01:06:34 PM PDT 24 |
Mar 12 01:06:49 PM PDT 24 |
107707500 ps |
| T251 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3436174771 |
|
|
Mar 12 01:06:10 PM PDT 24 |
Mar 12 01:13:57 PM PDT 24 |
460233700 ps |
| T1157 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2827857632 |
|
|
Mar 12 01:06:27 PM PDT 24 |
Mar 12 01:06:41 PM PDT 24 |
15806400 ps |
| T1158 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.491174746 |
|
|
Mar 12 01:06:21 PM PDT 24 |
Mar 12 01:06:35 PM PDT 24 |
16982800 ps |
| T285 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3979621025 |
|
|
Mar 12 01:06:38 PM PDT 24 |
Mar 12 01:07:14 PM PDT 24 |
217238300 ps |
| T1159 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1367542557 |
|
|
Mar 12 01:06:27 PM PDT 24 |
Mar 12 01:06:41 PM PDT 24 |
56541400 ps |
| T1160 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4073935849 |
|
|
Mar 12 01:06:12 PM PDT 24 |
Mar 12 01:06:29 PM PDT 24 |
36373400 ps |
| T1161 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.490957263 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:31 PM PDT 24 |
29103700 ps |
| T1162 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1686957238 |
|
|
Mar 12 01:06:29 PM PDT 24 |
Mar 12 01:06:47 PM PDT 24 |
61706600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3426782347 |
|
|
Mar 12 01:06:28 PM PDT 24 |
Mar 12 01:06:45 PM PDT 24 |
159947000 ps |
| T248 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.164158459 |
|
|
Mar 12 01:06:27 PM PDT 24 |
Mar 12 01:06:43 PM PDT 24 |
114655400 ps |
| T286 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2682335616 |
|
|
Mar 12 01:06:34 PM PDT 24 |
Mar 12 01:07:05 PM PDT 24 |
181264400 ps |
| T1164 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2050135355 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:06:45 PM PDT 24 |
17997600 ps |
| T1165 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1568058429 |
|
|
Mar 12 01:06:19 PM PDT 24 |
Mar 12 01:06:57 PM PDT 24 |
26098200 ps |
| T250 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3669161173 |
|
|
Mar 12 01:06:11 PM PDT 24 |
Mar 12 01:06:28 PM PDT 24 |
60849200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2631570448 |
|
|
Mar 12 01:06:50 PM PDT 24 |
Mar 12 01:07:05 PM PDT 24 |
22470600 ps |
| T287 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3495903979 |
|
|
Mar 12 01:06:46 PM PDT 24 |
Mar 12 01:07:01 PM PDT 24 |
382412500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.525337504 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:06:47 PM PDT 24 |
14760600 ps |
| T288 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.480061848 |
|
|
Mar 12 01:06:33 PM PDT 24 |
Mar 12 01:12:56 PM PDT 24 |
847874600 ps |
| T309 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.330233423 |
|
|
Mar 12 01:06:23 PM PDT 24 |
Mar 12 01:06:44 PM PDT 24 |
179690100 ps |
| T225 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.129956646 |
|
|
Mar 12 01:06:04 PM PDT 24 |
Mar 12 01:06:18 PM PDT 24 |
42324800 ps |
| T1168 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2514720368 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:06:34 PM PDT 24 |
38336100 ps |
| T1169 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.318892908 |
|
|
Mar 12 01:06:25 PM PDT 24 |
Mar 12 01:06:42 PM PDT 24 |
43520100 ps |
| T1170 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1875865721 |
|
|
Mar 12 01:06:22 PM PDT 24 |
Mar 12 01:06:57 PM PDT 24 |
160889300 ps |
| T1171 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2732130253 |
|
|
Mar 12 01:06:22 PM PDT 24 |
Mar 12 01:06:39 PM PDT 24 |
43250900 ps |
| T1172 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3601713277 |
|
|
Mar 12 01:06:38 PM PDT 24 |
Mar 12 01:06:52 PM PDT 24 |
30190600 ps |
| T1173 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3031275867 |
|
|
Mar 12 01:06:31 PM PDT 24 |
Mar 12 01:06:45 PM PDT 24 |
90212400 ps |
| T1174 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1011818656 |
|
|
Mar 12 01:06:04 PM PDT 24 |
Mar 12 01:06:19 PM PDT 24 |
145669300 ps |
| T1175 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1970614250 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:06:29 PM PDT 24 |
12221700 ps |
| T1176 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3264073581 |
|
|
Mar 12 01:06:13 PM PDT 24 |
Mar 12 01:06:29 PM PDT 24 |
18143500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1751293237 |
|
|
Mar 12 01:06:13 PM PDT 24 |
Mar 12 01:06:26 PM PDT 24 |
21733100 ps |
| T1178 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1868917196 |
|
|
Mar 12 01:06:40 PM PDT 24 |
Mar 12 01:06:54 PM PDT 24 |
17509000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3113471247 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:06:30 PM PDT 24 |
26344700 ps |
| T1180 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4127334544 |
|
|
Mar 12 01:06:27 PM PDT 24 |
Mar 12 01:06:43 PM PDT 24 |
25256700 ps |
| T255 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3147248407 |
|
|
Mar 12 01:06:28 PM PDT 24 |
Mar 12 01:12:49 PM PDT 24 |
369979700 ps |
| T1181 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3582867474 |
|
|
Mar 12 01:06:43 PM PDT 24 |
Mar 12 01:06:56 PM PDT 24 |
46063200 ps |
| T1182 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.4259691091 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:51 PM PDT 24 |
29868600 ps |
| T259 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1504427498 |
|
|
Mar 12 01:06:22 PM PDT 24 |
Mar 12 01:21:16 PM PDT 24 |
3163190700 ps |
| T1183 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3255772359 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:06:32 PM PDT 24 |
20588800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.4109145561 |
|
|
Mar 12 01:06:12 PM PDT 24 |
Mar 12 01:07:03 PM PDT 24 |
826015600 ps |
| T1185 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1100312106 |
|
|
Mar 12 01:06:34 PM PDT 24 |
Mar 12 01:06:48 PM PDT 24 |
25492500 ps |
| T289 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.338130785 |
|
|
Mar 12 01:06:15 PM PDT 24 |
Mar 12 01:14:03 PM PDT 24 |
1261264900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2828195840 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:06:31 PM PDT 24 |
41086800 ps |
| T253 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3173590571 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:37 PM PDT 24 |
964300500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1385513929 |
|
|
Mar 12 01:06:47 PM PDT 24 |
Mar 12 01:07:02 PM PDT 24 |
15432000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.427888266 |
|
|
Mar 12 01:06:35 PM PDT 24 |
Mar 12 01:06:48 PM PDT 24 |
141033000 ps |
| T290 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2216565307 |
|
|
Mar 12 01:06:12 PM PDT 24 |
Mar 12 01:06:31 PM PDT 24 |
81053400 ps |
| T291 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.640964873 |
|
|
Mar 12 01:06:20 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
180485000 ps |
| T1189 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.547121164 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:06:36 PM PDT 24 |
57961300 ps |
| T1190 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.4211881924 |
|
|
Mar 12 01:06:44 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
17822300 ps |
| T1191 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1739241994 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:53 PM PDT 24 |
14731500 ps |
| T1192 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.11650657 |
|
|
Mar 12 01:06:41 PM PDT 24 |
Mar 12 01:06:56 PM PDT 24 |
27680600 ps |
| T1193 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2709008296 |
|
|
Mar 12 01:06:21 PM PDT 24 |
Mar 12 01:06:40 PM PDT 24 |
230410100 ps |
| T247 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2194073731 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:37 PM PDT 24 |
177597100 ps |
| T1194 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.275185870 |
|
|
Mar 12 01:06:34 PM PDT 24 |
Mar 12 01:06:52 PM PDT 24 |
145842700 ps |
| T1195 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3053683880 |
|
|
Mar 12 01:06:42 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
82518900 ps |
| T337 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2659336473 |
|
|
Mar 12 01:06:15 PM PDT 24 |
Mar 12 01:06:32 PM PDT 24 |
79248800 ps |
| T1196 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2244798745 |
|
|
Mar 12 01:06:50 PM PDT 24 |
Mar 12 01:07:04 PM PDT 24 |
49440700 ps |
| T1197 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1840129503 |
|
|
Mar 12 01:06:31 PM PDT 24 |
Mar 12 01:06:51 PM PDT 24 |
320119000 ps |
| T293 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3091731420 |
|
|
Mar 12 01:06:45 PM PDT 24 |
Mar 12 01:07:03 PM PDT 24 |
202837100 ps |
| T294 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1644585752 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
2983930700 ps |
| T1198 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2772195600 |
|
|
Mar 12 01:06:04 PM PDT 24 |
Mar 12 01:07:30 PM PDT 24 |
13130845200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.43390383 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:36 PM PDT 24 |
347990500 ps |
| T1200 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.4120152938 |
|
|
Mar 12 01:06:34 PM PDT 24 |
Mar 12 01:06:48 PM PDT 24 |
18143900 ps |
| T1201 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1503532046 |
|
|
Mar 12 01:06:20 PM PDT 24 |
Mar 12 01:06:36 PM PDT 24 |
12277000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1253350940 |
|
|
Mar 12 01:06:21 PM PDT 24 |
Mar 12 01:06:37 PM PDT 24 |
163176800 ps |
| T1203 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.256774148 |
|
|
Mar 12 01:06:42 PM PDT 24 |
Mar 12 01:06:56 PM PDT 24 |
17945200 ps |
| T256 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2246807415 |
|
|
Mar 12 01:06:27 PM PDT 24 |
Mar 12 01:21:31 PM PDT 24 |
7359735000 ps |
| T1204 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3907577824 |
|
|
Mar 12 01:06:25 PM PDT 24 |
Mar 12 01:06:44 PM PDT 24 |
314800900 ps |
| T1205 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3542359967 |
|
|
Mar 12 01:06:44 PM PDT 24 |
Mar 12 01:06:58 PM PDT 24 |
12187600 ps |
| T1206 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1080687332 |
|
|
Mar 12 01:06:43 PM PDT 24 |
Mar 12 01:07:03 PM PDT 24 |
352484900 ps |
| T1207 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1198461362 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:06:46 PM PDT 24 |
18876800 ps |
| T254 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.864486015 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:54 PM PDT 24 |
30418300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2563910856 |
|
|
Mar 12 01:06:39 PM PDT 24 |
Mar 12 01:06:57 PM PDT 24 |
152097500 ps |
| T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1574729805 |
|
|
Mar 12 01:06:03 PM PDT 24 |
Mar 12 01:06:21 PM PDT 24 |
40052900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2191985672 |
|
|
Mar 12 01:06:14 PM PDT 24 |
Mar 12 01:06:33 PM PDT 24 |
160082800 ps |
| T226 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2900650113 |
|
|
Mar 12 01:06:15 PM PDT 24 |
Mar 12 01:06:28 PM PDT 24 |
59887500 ps |
| T1211 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.613963911 |
|
|
Mar 12 01:06:19 PM PDT 24 |
Mar 12 01:06:32 PM PDT 24 |
17487000 ps |
| T339 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1768874296 |
|
|
Mar 12 01:06:29 PM PDT 24 |
Mar 12 01:14:09 PM PDT 24 |
718107900 ps |
| T1212 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3162230685 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:08:17 PM PDT 24 |
38321717900 ps |
| T243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.504307446 |
|
|
Mar 12 01:06:09 PM PDT 24 |
Mar 12 01:06:25 PM PDT 24 |
33051100 ps |
| T1213 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1983594897 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:07:08 PM PDT 24 |
1681729300 ps |
| T1214 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2846195425 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:06:32 PM PDT 24 |
23999300 ps |
| T1215 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2134415368 |
|
|
Mar 12 01:06:13 PM PDT 24 |
Mar 12 01:06:47 PM PDT 24 |
1082727500 ps |
| T345 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3042732192 |
|
|
Mar 12 01:06:27 PM PDT 24 |
Mar 12 01:21:16 PM PDT 24 |
1393856700 ps |
| T1216 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.4048258011 |
|
|
Mar 12 01:06:40 PM PDT 24 |
Mar 12 01:06:54 PM PDT 24 |
29351100 ps |
| T340 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.420886575 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:18:49 PM PDT 24 |
1253698800 ps |
| T1217 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3611165734 |
|
|
Mar 12 01:06:14 PM PDT 24 |
Mar 12 01:06:29 PM PDT 24 |
123437300 ps |
| T343 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2616901773 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:19:03 PM PDT 24 |
3150350100 ps |
| T1218 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.211061875 |
|
|
Mar 12 01:06:24 PM PDT 24 |
Mar 12 01:06:37 PM PDT 24 |
18641500 ps |
| T1219 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4264970112 |
|
|
Mar 12 01:06:13 PM PDT 24 |
Mar 12 01:06:27 PM PDT 24 |
15057400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2812780092 |
|
|
Mar 12 01:06:31 PM PDT 24 |
Mar 12 01:06:49 PM PDT 24 |
39687900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4293569620 |
|
|
Mar 12 01:06:11 PM PDT 24 |
Mar 12 01:06:27 PM PDT 24 |
43307500 ps |
| T1222 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1718310541 |
|
|
Mar 12 01:06:47 PM PDT 24 |
Mar 12 01:07:03 PM PDT 24 |
42585600 ps |
| T1223 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.301218751 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:52 PM PDT 24 |
15879200 ps |
| T1224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2521518292 |
|
|
Mar 12 01:06:06 PM PDT 24 |
Mar 12 01:06:24 PM PDT 24 |
61231900 ps |
| T342 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4041110664 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:12:39 PM PDT 24 |
406332800 ps |
| T295 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2778363628 |
|
|
Mar 12 01:06:15 PM PDT 24 |
Mar 12 01:06:30 PM PDT 24 |
233885600 ps |
| T347 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1627772129 |
|
|
Mar 12 01:06:03 PM PDT 24 |
Mar 12 01:21:03 PM PDT 24 |
1418093400 ps |
| T1225 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2200937963 |
|
|
Mar 12 01:06:28 PM PDT 24 |
Mar 12 01:06:46 PM PDT 24 |
61478100 ps |
| T1226 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2058336697 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:07:24 PM PDT 24 |
4162562700 ps |
| T296 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1654974579 |
|
|
Mar 12 01:06:12 PM PDT 24 |
Mar 12 01:06:32 PM PDT 24 |
403333000 ps |
| T1227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3851922164 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:06:33 PM PDT 24 |
38758200 ps |
| T1228 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4036053449 |
|
|
Mar 12 01:06:15 PM PDT 24 |
Mar 12 01:06:29 PM PDT 24 |
12399900 ps |
| T1229 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3798297539 |
|
|
Mar 12 01:06:19 PM PDT 24 |
Mar 12 01:06:35 PM PDT 24 |
57090400 ps |
| T1230 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2709469665 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:53 PM PDT 24 |
13146300 ps |
| T1231 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1646557907 |
|
|
Mar 12 01:06:29 PM PDT 24 |
Mar 12 01:06:45 PM PDT 24 |
278954400 ps |
| T1232 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2243477785 |
|
|
Mar 12 01:06:33 PM PDT 24 |
Mar 12 01:06:47 PM PDT 24 |
118299600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.893016615 |
|
|
Mar 12 01:06:40 PM PDT 24 |
Mar 12 01:06:54 PM PDT 24 |
26240700 ps |
| T1234 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3761810761 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:55 PM PDT 24 |
100657100 ps |
| T1235 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3373433030 |
|
|
Mar 12 01:06:43 PM PDT 24 |
Mar 12 01:06:57 PM PDT 24 |
16993400 ps |
| T258 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3652575479 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:35 PM PDT 24 |
205200600 ps |
| T1236 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.77882329 |
|
|
Mar 12 01:06:15 PM PDT 24 |
Mar 12 01:06:35 PM PDT 24 |
187379500 ps |
| T1237 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2690799942 |
|
|
Mar 12 01:06:17 PM PDT 24 |
Mar 12 01:06:32 PM PDT 24 |
17488100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1120629021 |
|
|
Mar 12 01:06:37 PM PDT 24 |
Mar 12 01:06:50 PM PDT 24 |
55786700 ps |
| T1239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1583664329 |
|
|
Mar 12 01:06:26 PM PDT 24 |
Mar 12 01:06:40 PM PDT 24 |
55189400 ps |
| T1240 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.67427100 |
|
|
Mar 12 01:06:29 PM PDT 24 |
Mar 12 01:06:43 PM PDT 24 |
17635400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3287345186 |
|
|
Mar 12 01:06:11 PM PDT 24 |
Mar 12 01:06:30 PM PDT 24 |
50108900 ps |
| T1242 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2209395844 |
|
|
Mar 12 01:06:20 PM PDT 24 |
Mar 12 01:06:37 PM PDT 24 |
209135400 ps |
| T1243 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1975113162 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:06:47 PM PDT 24 |
39360000 ps |
| T1244 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.4056655649 |
|
|
Mar 12 01:06:40 PM PDT 24 |
Mar 12 01:06:54 PM PDT 24 |
48217900 ps |
| T1245 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1419581504 |
|
|
Mar 12 01:06:18 PM PDT 24 |
Mar 12 01:06:34 PM PDT 24 |
28710200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2809339824 |
|
|
Mar 12 01:06:26 PM PDT 24 |
Mar 12 01:06:45 PM PDT 24 |
159232300 ps |
| T1247 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2424989352 |
|
|
Mar 12 01:06:36 PM PDT 24 |
Mar 12 01:06:50 PM PDT 24 |
44279900 ps |
| T1248 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4057715027 |
|
|
Mar 12 01:06:35 PM PDT 24 |
Mar 12 01:06:50 PM PDT 24 |
16898500 ps |
| T297 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2107386906 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:06:35 PM PDT 24 |
514417000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3976184551 |
|
|
Mar 12 01:06:35 PM PDT 24 |
Mar 12 01:06:49 PM PDT 24 |
31789600 ps |
| T346 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.556813651 |
|
|
Mar 12 01:06:48 PM PDT 24 |
Mar 12 01:19:38 PM PDT 24 |
830463000 ps |
| T227 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2402606802 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:06:30 PM PDT 24 |
18679600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4215078232 |
|
|
Mar 12 01:06:43 PM PDT 24 |
Mar 12 01:06:56 PM PDT 24 |
17433800 ps |
| T1251 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2179168416 |
|
|
Mar 12 01:06:30 PM PDT 24 |
Mar 12 01:06:47 PM PDT 24 |
15002600 ps |
| T252 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1250965357 |
|
|
Mar 12 01:06:32 PM PDT 24 |
Mar 12 01:06:51 PM PDT 24 |
110583200 ps |
| T1252 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.376724504 |
|
|
Mar 12 01:06:45 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
52191800 ps |
| T1253 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.710625333 |
|
|
Mar 12 01:06:40 PM PDT 24 |
Mar 12 01:06:56 PM PDT 24 |
95532700 ps |
| T298 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.139581474 |
|
|
Mar 12 01:06:11 PM PDT 24 |
Mar 12 01:06:59 PM PDT 24 |
815909500 ps |
| T1254 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1887812074 |
|
|
Mar 12 01:06:32 PM PDT 24 |
Mar 12 01:06:46 PM PDT 24 |
57189100 ps |
| T338 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3716013523 |
|
|
Mar 12 01:06:16 PM PDT 24 |
Mar 12 01:06:36 PM PDT 24 |
43420800 ps |
| T1255 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4187976429 |
|
|
Mar 12 01:06:31 PM PDT 24 |
Mar 12 01:06:47 PM PDT 24 |
190719400 ps |
| T1256 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1262415459 |
|
|
Mar 12 01:06:51 PM PDT 24 |
Mar 12 01:07:07 PM PDT 24 |
16478400 ps |