Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	325880	1		T1	1781		T2	1		T3	1
all_values[1]	325880	1		T1	1781		T2	1		T3	1
all_values[2]	325880	1		T1	1781		T2	1		T3	1
all_values[3]	325880	1		T1	1781		T2	1		T3	1
all_values[4]	325880	1		T1	1781		T2	1		T3	1
all_values[5]	325880	1		T1	1781		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	658268	1		T1	3566		T2	6		T3	6
auto[1]	1297012	1		T1	7120		T4	5440		T33	80424

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	958279	1		T1	5344		T2	4		T3	4
auto[1]	997001	1		T1	5342		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	325724	1		T1	1781		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	156	1		T275	4		T276	2		T332	1
all_values[1]	auto[0]	auto[1]	325732	1		T1	1781		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	148	1		T275	2		T277	6		T332	6
all_values[2]	auto[0]	auto[0]	1641	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	54	1		T275	1		T276	2		T277	1
all_values[2]	auto[1]	auto[0]	324132	1		T1	1780		T4	1360		T33	20106
all_values[2]	auto[1]	auto[1]	53	1		T275	1		T276	3		T277	2
all_values[3]	auto[0]	auto[0]	1656	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	64	1		T276	1		T277	3		T333	2
all_values[3]	auto[1]	auto[0]	77456	1		T1	890		T4	680		T32	1173
all_values[3]	auto[1]	auto[1]	246704	1		T1	890		T4	680		T33	20106
all_values[4]	auto[0]	auto[0]	1157	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	544	1		T5	1		T7	3		T14	1
all_values[4]	auto[1]	auto[0]	226551	1		T1	890		T4	680		T33	19320
all_values[4]	auto[1]	auto[1]	97628	1		T1	890		T4	680		T33	786
all_values[5]	auto[0]	auto[0]	1558	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	138	1		T35	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	324128	1		T1	1780		T4	1360		T33	20106
all_values[5]	auto[1]	auto[1]	56	1		T275	3		T332	2		T343	1