Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T5 |
7 |
|
T386 |
1 |
|
T380 |
1 |
| others[1] |
200 |
1 |
|
T5 |
8 |
|
T267 |
1 |
|
T31 |
11 |
| others[2] |
218 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T73 |
1 |
| others[3] |
397 |
1 |
|
T5 |
18 |
|
T140 |
1 |
|
T380 |
1 |
| false |
121 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T31 |
3 |
| true |
12649 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T12 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8178 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T5 |
15 |
| others[1] |
1206 |
1 |
|
T20 |
1 |
|
T5 |
20 |
|
T7 |
1 |
| others[2] |
1205 |
1 |
|
T5 |
21 |
|
T8 |
9 |
|
T33 |
1 |
| others[3] |
2105 |
1 |
|
T5 |
32 |
|
T7 |
3 |
|
T8 |
18 |
| false |
675 |
1 |
|
T5 |
13 |
|
T8 |
2 |
|
T47 |
2 |
| true |
451 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8182 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T5 |
16 |
| others[1] |
1249 |
1 |
|
T19 |
1 |
|
T5 |
18 |
|
T7 |
1 |
| others[2] |
1249 |
1 |
|
T5 |
24 |
|
T8 |
9 |
|
T47 |
7 |
| others[3] |
2060 |
1 |
|
T20 |
1 |
|
T5 |
36 |
|
T7 |
1 |
| false |
649 |
1 |
|
T5 |
7 |
|
T7 |
1 |
|
T8 |
4 |
| true |
431 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T5 |
4 |
|
T7 |
2 |
|
T31 |
3 |
| others[1] |
108 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T380 |
1 |
| others[2] |
108 |
1 |
|
T5 |
7 |
|
T77 |
1 |
|
T380 |
1 |
| others[3] |
193 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T383 |
1 |
| false |
59 |
1 |
|
T5 |
1 |
|
T31 |
3 |
|
T124 |
2 |
| true |
13260 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T12 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T1 |
1 |
|
T5 |
7 |
|
T219 |
1 |
| others[1] |
242 |
1 |
|
T6 |
1 |
|
T5 |
9 |
|
T7 |
1 |
| others[2] |
238 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T31 |
9 |
| others[3] |
412 |
1 |
|
T5 |
19 |
|
T7 |
1 |
|
T40 |
1 |
| false |
145 |
1 |
|
T5 |
6 |
|
T386 |
1 |
|
T382 |
1 |
| true |
12547 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8031 |
1 |
|
T12 |
2 |
|
T20 |
1 |
|
T5 |
17 |
| others[1] |
1089 |
1 |
|
T6 |
1 |
|
T5 |
23 |
|
T7 |
1 |
| others[2] |
1083 |
1 |
|
T19 |
1 |
|
T5 |
12 |
|
T7 |
1 |
| others[3] |
1786 |
1 |
|
T4 |
1 |
|
T5 |
38 |
|
T7 |
2 |
| false |
527 |
1 |
|
T5 |
11 |
|
T8 |
4 |
|
T47 |
3 |
| true |
1304 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T243 |
1 |
| others[1] |
220 |
1 |
|
T5 |
13 |
|
T31 |
7 |
|
T385 |
1 |
| others[2] |
195 |
1 |
|
T5 |
8 |
|
T230 |
1 |
|
T120 |
1 |
| others[3] |
379 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T32 |
1 |
| false |
122 |
1 |
|
T5 |
7 |
|
T7 |
1 |
|
T386 |
1 |
| true |
12672 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T12 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T31 |
13 |
| others[1] |
236 |
1 |
|
T5 |
12 |
|
T7 |
1 |
|
T77 |
1 |
| others[2] |
236 |
1 |
|
T5 |
6 |
|
T40 |
1 |
|
T31 |
14 |
| others[3] |
364 |
1 |
|
T5 |
14 |
|
T73 |
1 |
|
T380 |
1 |
| false |
94 |
1 |
|
T31 |
3 |
|
T124 |
5 |
|
T210 |
1 |
| true |
12640 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T12 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8138 |
1 |
|
T12 |
2 |
|
T5 |
21 |
|
T7 |
1 |
| others[1] |
1271 |
1 |
|
T20 |
1 |
|
T5 |
14 |
|
T7 |
2 |
| others[2] |
1251 |
1 |
|
T5 |
19 |
|
T8 |
11 |
|
T47 |
12 |
| others[3] |
2085 |
1 |
|
T4 |
1 |
|
T5 |
36 |
|
T8 |
17 |
| false |
640 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T8 |
4 |
| true |
435 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1201 |
1 |
|
T5 |
16 |
|
T8 |
10 |
|
T47 |
13 |
| others[1] |
1297 |
1 |
|
T5 |
27 |
|
T7 |
1 |
|
T13 |
1 |
| others[2] |
1239 |
1 |
|
T5 |
17 |
|
T7 |
2 |
|
T8 |
11 |
| others[3] |
2059 |
1 |
|
T4 |
1 |
|
T5 |
27 |
|
T7 |
1 |
| false |
640 |
1 |
|
T20 |
1 |
|
T5 |
14 |
|
T8 |
6 |
| true |
428 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
96 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T380 |
1 |
| others[1] |
125 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T140 |
1 |
| others[2] |
109 |
1 |
|
T5 |
5 |
|
T31 |
4 |
|
T381 |
1 |
| others[3] |
207 |
1 |
|
T5 |
9 |
|
T7 |
2 |
|
T73 |
1 |
| false |
55 |
1 |
|
T5 |
1 |
|
T31 |
3 |
|
T124 |
1 |
| true |
6272 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T5 |
9 |
|
T7 |
2 |
|
T26 |
1 |
| others[1] |
229 |
1 |
|
T5 |
9 |
|
T289 |
1 |
|
T49 |
1 |
| others[2] |
236 |
1 |
|
T5 |
11 |
|
T25 |
1 |
|
T380 |
1 |
| others[3] |
416 |
1 |
|
T5 |
17 |
|
T32 |
1 |
|
T73 |
1 |
| false |
133 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T31 |
7 |
| true |
5602 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T5 |
24 |
|
T8 |
7 |
|
T33 |
1 |
| others[1] |
1065 |
1 |
|
T20 |
1 |
|
T5 |
15 |
|
T7 |
1 |
| others[2] |
1109 |
1 |
|
T5 |
25 |
|
T7 |
2 |
|
T8 |
13 |
| others[3] |
1688 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T5 |
26 |
| false |
526 |
1 |
|
T5 |
11 |
|
T8 |
9 |
|
T47 |
2 |
| true |
1403 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T5 |
9 |
|
T73 |
1 |
|
T65 |
1 |
| others[1] |
249 |
1 |
|
T6 |
1 |
|
T5 |
17 |
|
T34 |
1 |
| others[2] |
224 |
1 |
|
T1 |
1 |
|
T5 |
10 |
|
T7 |
3 |
| others[3] |
400 |
1 |
|
T5 |
12 |
|
T32 |
1 |
|
T138 |
1 |
| false |
105 |
1 |
|
T5 |
6 |
|
T31 |
7 |
|
T221 |
1 |
| true |
5664 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T5 |
9 |
|
T31 |
11 |
|
T385 |
1 |
| others[1] |
229 |
1 |
|
T5 |
20 |
|
T140 |
1 |
|
T31 |
11 |
| others[2] |
208 |
1 |
|
T5 |
9 |
|
T40 |
1 |
|
T382 |
1 |
| others[3] |
353 |
1 |
|
T5 |
19 |
|
T73 |
1 |
|
T31 |
14 |
| false |
104 |
1 |
|
T5 |
5 |
|
T77 |
1 |
|
T386 |
1 |
| true |
5744 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
13 |
| others[1] |
1179 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T8 |
7 |
| others[2] |
1257 |
1 |
|
T5 |
27 |
|
T8 |
15 |
|
T33 |
1 |
| others[3] |
2097 |
1 |
|
T5 |
29 |
|
T7 |
3 |
|
T8 |
14 |
| false |
659 |
1 |
|
T5 |
14 |
|
T8 |
4 |
|
T47 |
4 |
| true |
449 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T5 |
18 |
|
T8 |
8 |
|
T47 |
7 |
| others[1] |
1273 |
1 |
|
T5 |
24 |
|
T7 |
1 |
|
T8 |
10 |
| others[2] |
1270 |
1 |
|
T5 |
11 |
|
T7 |
2 |
|
T8 |
11 |
| others[3] |
2025 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
| false |
619 |
1 |
|
T5 |
6 |
|
T8 |
7 |
|
T47 |
2 |
| true |
428 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T5 |
4 |
|
T31 |
4 |
|
T207 |
1 |
| others[1] |
102 |
1 |
|
T5 |
3 |
|
T7 |
2 |
|
T77 |
1 |
| others[2] |
97 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T31 |
2 |
| others[3] |
194 |
1 |
|
T5 |
11 |
|
T380 |
1 |
|
T31 |
6 |
| false |
54 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T380 |
1 |
| true |
6313 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T34 |
1 |
| others[1] |
223 |
1 |
|
T5 |
11 |
|
T26 |
1 |
|
T383 |
1 |
| others[2] |
243 |
1 |
|
T5 |
8 |
|
T24 |
1 |
|
T138 |
1 |
| others[3] |
404 |
1 |
|
T5 |
21 |
|
T7 |
1 |
|
T40 |
1 |
| false |
109 |
1 |
|
T5 |
2 |
|
T25 |
1 |
|
T65 |
1 |
| true |
5650 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1064 |
1 |
|
T5 |
18 |
|
T8 |
8 |
|
T24 |
1 |
| others[1] |
1047 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
19 |
| others[2] |
1006 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T13 |
1 |
| others[3] |
1740 |
1 |
|
T5 |
33 |
|
T7 |
2 |
|
T8 |
20 |
| false |
551 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T8 |
5 |
| true |
1456 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T5 |
9 |
|
T34 |
1 |
|
T386 |
1 |
| others[1] |
237 |
1 |
|
T6 |
1 |
|
T5 |
22 |
|
T7 |
1 |
| others[2] |
235 |
1 |
|
T5 |
8 |
|
T7 |
2 |
|
T24 |
1 |
| others[3] |
394 |
1 |
|
T5 |
13 |
|
T77 |
1 |
|
T267 |
1 |
| false |
119 |
1 |
|
T5 |
6 |
|
T140 |
1 |
|
T243 |
1 |
| true |
5638 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T5 |
11 |
|
T31 |
17 |
|
T124 |
10 |
| others[1] |
244 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T140 |
1 |
| others[2] |
197 |
1 |
|
T5 |
11 |
|
T382 |
1 |
|
T31 |
11 |
| others[3] |
373 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T383 |
1 |
| false |
125 |
1 |
|
T5 |
2 |
|
T31 |
3 |
|
T124 |
4 |
| true |
5686 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T4 |
1 |
|
T5 |
19 |
|
T7 |
2 |
| others[1] |
1243 |
1 |
|
T5 |
20 |
|
T8 |
11 |
|
T47 |
9 |
| others[2] |
1262 |
1 |
|
T5 |
19 |
|
T7 |
1 |
|
T8 |
13 |
| others[3] |
2066 |
1 |
|
T20 |
1 |
|
T5 |
37 |
|
T8 |
8 |
| false |
654 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T8 |
6 |
| true |
435 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T4 |
1 |
|
T5 |
20 |
|
T7 |
2 |
| others[1] |
1242 |
1 |
|
T5 |
23 |
|
T7 |
1 |
|
T8 |
7 |
| others[2] |
1232 |
1 |
|
T5 |
21 |
|
T8 |
7 |
|
T47 |
6 |
| others[3] |
2096 |
1 |
|
T20 |
1 |
|
T5 |
28 |
|
T7 |
1 |
| false |
616 |
1 |
|
T5 |
9 |
|
T8 |
5 |
|
T33 |
1 |
| true |
435 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T5 |
5 |
|
T380 |
2 |
|
T31 |
1 |
| others[1] |
94 |
1 |
|
T5 |
5 |
|
T7 |
3 |
|
T383 |
1 |
| others[2] |
112 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T31 |
3 |
| others[3] |
191 |
1 |
|
T5 |
8 |
|
T77 |
1 |
|
T31 |
7 |
| false |
52 |
1 |
|
T31 |
1 |
|
T385 |
1 |
|
T124 |
2 |
| true |
6306 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T5 |
11 |
|
T77 |
1 |
|
T267 |
1 |
| others[1] |
245 |
1 |
|
T5 |
8 |
|
T24 |
1 |
|
T140 |
1 |
| others[2] |
239 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T230 |
1 |
| others[3] |
399 |
1 |
|
T5 |
16 |
|
T25 |
1 |
|
T34 |
1 |
| false |
118 |
1 |
|
T5 |
5 |
|
T65 |
1 |
|
T220 |
1 |
| true |
5631 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1028 |
1 |
|
T1 |
1 |
|
T5 |
20 |
|
T7 |
2 |
| others[1] |
1049 |
1 |
|
T6 |
1 |
|
T5 |
17 |
|
T7 |
1 |
| others[2] |
1042 |
1 |
|
T5 |
20 |
|
T13 |
1 |
|
T8 |
12 |
| others[3] |
1835 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
33 |
| false |
509 |
1 |
|
T5 |
11 |
|
T8 |
3 |
|
T24 |
1 |
| true |
1401 |
1 |
|
T19 |
1 |
|
T14 |
1 |
|
T156 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
257 |
1 |
|
T6 |
1 |
|
T5 |
13 |
|
T7 |
2 |
| others[1] |
230 |
1 |
|
T5 |
5 |
|
T140 |
1 |
|
T31 |
3 |
| others[2] |
224 |
1 |
|
T5 |
6 |
|
T383 |
1 |
|
T31 |
9 |
| others[3] |
349 |
1 |
|
T5 |
18 |
|
T24 |
1 |
|
T34 |
1 |
| false |
126 |
1 |
|
T5 |
8 |
|
T119 |
1 |
|
T380 |
1 |
| true |
5678 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T5 |
6 |
|
T386 |
1 |
|
T383 |
1 |
| others[1] |
216 |
1 |
|
T5 |
14 |
|
T31 |
6 |
|
T385 |
1 |
| others[2] |
241 |
1 |
|
T5 |
13 |
|
T380 |
1 |
|
T31 |
12 |
| others[3] |
362 |
1 |
|
T5 |
16 |
|
T7 |
1 |
|
T73 |
1 |
| false |
118 |
1 |
|
T5 |
2 |
|
T31 |
5 |
|
T124 |
9 |
| true |
5704 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T20 |
1 |
|
T5 |
23 |
|
T7 |
1 |
| others[1] |
1254 |
1 |
|
T19 |
1 |
|
T5 |
14 |
|
T8 |
7 |
| others[2] |
1274 |
1 |
|
T1 |
1 |
|
T5 |
18 |
|
T8 |
10 |
| others[3] |
2013 |
1 |
|
T4 |
1 |
|
T5 |
37 |
|
T7 |
3 |
| false |
634 |
1 |
|
T5 |
9 |
|
T8 |
4 |
|
T47 |
1 |
| true |
450 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T20 |
1 |
|
T5 |
26 |
|
T8 |
7 |
| others[1] |
1235 |
1 |
|
T5 |
15 |
|
T7 |
2 |
|
T8 |
8 |
| others[2] |
1231 |
1 |
|
T5 |
21 |
|
T8 |
10 |
|
T47 |
7 |
| others[3] |
2054 |
1 |
|
T4 |
1 |
|
T5 |
34 |
|
T7 |
2 |
| false |
649 |
1 |
|
T5 |
5 |
|
T13 |
1 |
|
T8 |
7 |
| true |
428 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |