Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T380 |
2 |
| others[1] |
115 |
1 |
|
T5 |
7 |
|
T31 |
5 |
|
T207 |
2 |
| others[2] |
89 |
1 |
|
T5 |
2 |
|
T40 |
1 |
|
T73 |
1 |
| others[3] |
176 |
1 |
|
T5 |
6 |
|
T7 |
2 |
|
T383 |
1 |
| false |
49 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T77 |
1 |
| true |
6326 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T65 |
1 |
| others[1] |
242 |
1 |
|
T5 |
10 |
|
T25 |
1 |
|
T386 |
1 |
| others[2] |
244 |
1 |
|
T6 |
1 |
|
T5 |
11 |
|
T7 |
2 |
| others[3] |
415 |
1 |
|
T1 |
1 |
|
T5 |
17 |
|
T31 |
23 |
| false |
141 |
1 |
|
T5 |
7 |
|
T32 |
1 |
|
T138 |
1 |
| true |
5569 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1083 |
1 |
|
T5 |
20 |
|
T7 |
1 |
|
T8 |
7 |
| others[1] |
1026 |
1 |
|
T1 |
1 |
|
T5 |
19 |
|
T7 |
1 |
| others[2] |
994 |
1 |
|
T5 |
18 |
|
T7 |
2 |
|
T8 |
8 |
| others[3] |
1818 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T20 |
1 |
| false |
554 |
1 |
|
T5 |
11 |
|
T8 |
10 |
|
T47 |
4 |
| true |
1389 |
1 |
|
T19 |
1 |
|
T14 |
1 |
|
T156 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T73 |
1 |
| others[1] |
230 |
1 |
|
T5 |
9 |
|
T77 |
1 |
|
T31 |
8 |
| others[2] |
215 |
1 |
|
T5 |
8 |
|
T383 |
1 |
|
T31 |
6 |
| others[3] |
403 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T34 |
1 |
| false |
121 |
1 |
|
T5 |
7 |
|
T138 |
1 |
|
T267 |
1 |
| true |
5683 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T383 |
1 |
| others[1] |
218 |
1 |
|
T5 |
11 |
|
T140 |
1 |
|
T386 |
1 |
| others[2] |
214 |
1 |
|
T5 |
7 |
|
T267 |
1 |
|
T382 |
1 |
| others[3] |
359 |
1 |
|
T5 |
15 |
|
T380 |
1 |
|
T31 |
14 |
| false |
113 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T31 |
8 |
| true |
5717 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1268 |
1 |
|
T20 |
1 |
|
T5 |
20 |
|
T8 |
7 |
| others[1] |
1178 |
1 |
|
T4 |
1 |
|
T5 |
27 |
|
T7 |
3 |
| others[2] |
1259 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T8 |
10 |
| others[3] |
2076 |
1 |
|
T5 |
27 |
|
T8 |
20 |
|
T33 |
1 |
| false |
643 |
1 |
|
T5 |
9 |
|
T8 |
4 |
|
T47 |
3 |
| true |
440 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T4 |
1 |
|
T5 |
17 |
|
T8 |
10 |
| others[1] |
1253 |
1 |
|
T5 |
23 |
|
T8 |
8 |
|
T47 |
4 |
| others[2] |
1271 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T5 |
20 |
| others[3] |
2044 |
1 |
|
T20 |
1 |
|
T5 |
31 |
|
T7 |
3 |
| false |
646 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T8 |
9 |
| true |
427 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T5 |
8 |
|
T380 |
1 |
|
T31 |
2 |
| others[1] |
99 |
1 |
|
T5 |
6 |
|
T77 |
1 |
|
T383 |
1 |
| others[2] |
114 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T31 |
3 |
| others[3] |
155 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T31 |
3 |
| false |
57 |
1 |
|
T5 |
6 |
|
T7 |
2 |
|
T31 |
1 |
| true |
6346 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T5 |
13 |
|
T140 |
1 |
|
T31 |
7 |
| others[1] |
234 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T138 |
1 |
| others[2] |
253 |
1 |
|
T1 |
1 |
|
T5 |
11 |
|
T34 |
1 |
| others[3] |
399 |
1 |
|
T5 |
10 |
|
T73 |
1 |
|
T26 |
1 |
| false |
104 |
1 |
|
T5 |
4 |
|
T24 |
1 |
|
T31 |
2 |
| true |
5626 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
974 |
1 |
|
T19 |
1 |
|
T5 |
12 |
|
T8 |
8 |
| others[1] |
1060 |
1 |
|
T6 |
1 |
|
T20 |
1 |
|
T5 |
16 |
| others[2] |
1124 |
1 |
|
T4 |
1 |
|
T5 |
21 |
|
T7 |
1 |
| others[3] |
1724 |
1 |
|
T5 |
37 |
|
T7 |
2 |
|
T8 |
13 |
| false |
568 |
1 |
|
T5 |
15 |
|
T8 |
8 |
|
T47 |
4 |
| true |
1414 |
1 |
|
T1 |
1 |
|
T25 |
1 |
|
T154 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T34 |
1 |
| others[1] |
249 |
1 |
|
T5 |
6 |
|
T77 |
1 |
|
T49 |
1 |
| others[2] |
244 |
1 |
|
T5 |
9 |
|
T40 |
1 |
|
T386 |
1 |
| others[3] |
416 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T24 |
1 |
| false |
106 |
1 |
|
T5 |
6 |
|
T120 |
1 |
|
T31 |
5 |
| true |
5616 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T5 |
11 |
|
T386 |
1 |
|
T31 |
6 |
| others[1] |
224 |
1 |
|
T5 |
13 |
|
T77 |
1 |
|
T380 |
1 |
| others[2] |
210 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T31 |
8 |
| others[3] |
368 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T380 |
1 |
| false |
126 |
1 |
|
T5 |
3 |
|
T40 |
1 |
|
T383 |
1 |
| true |
5687 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T5 |
18 |
|
T8 |
10 |
|
T47 |
9 |
| others[1] |
1264 |
1 |
|
T5 |
22 |
|
T7 |
1 |
|
T8 |
9 |
| others[2] |
1252 |
1 |
|
T4 |
1 |
|
T5 |
21 |
|
T8 |
13 |
| others[3] |
2029 |
1 |
|
T5 |
31 |
|
T7 |
3 |
|
T8 |
14 |
| false |
624 |
1 |
|
T20 |
1 |
|
T5 |
9 |
|
T8 |
4 |
| true |
439 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T5 |
21 |
|
T7 |
1 |
|
T8 |
7 |
| others[1] |
1246 |
1 |
|
T5 |
20 |
|
T7 |
1 |
|
T8 |
9 |
| others[2] |
1252 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T8 |
16 |
| others[3] |
2009 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
32 |
| false |
667 |
1 |
|
T1 |
1 |
|
T5 |
10 |
|
T8 |
5 |
| true |
432 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T383 |
1 |
| others[1] |
115 |
1 |
|
T5 |
5 |
|
T77 |
1 |
|
T140 |
1 |
| others[2] |
109 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T73 |
1 |
| others[3] |
182 |
1 |
|
T5 |
11 |
|
T7 |
2 |
|
T31 |
5 |
| false |
66 |
1 |
|
T5 |
3 |
|
T31 |
8 |
|
T259 |
1 |
| true |
6289 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T1 |
1 |
|
T5 |
10 |
|
T65 |
1 |
| others[1] |
245 |
1 |
|
T5 |
14 |
|
T73 |
1 |
|
T220 |
1 |
| others[2] |
240 |
1 |
|
T5 |
9 |
|
T386 |
1 |
|
T119 |
1 |
| others[3] |
382 |
1 |
|
T6 |
1 |
|
T5 |
17 |
|
T7 |
1 |
| false |
120 |
1 |
|
T5 |
5 |
|
T31 |
8 |
|
T124 |
3 |
| true |
5650 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1012 |
1 |
|
T5 |
15 |
|
T7 |
1 |
|
T8 |
13 |
| others[1] |
1045 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T5 |
19 |
| others[2] |
1080 |
1 |
|
T5 |
26 |
|
T8 |
9 |
|
T47 |
9 |
| others[3] |
1770 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T5 |
29 |
| false |
553 |
1 |
|
T5 |
12 |
|
T7 |
2 |
|
T8 |
4 |
| true |
1404 |
1 |
|
T1 |
1 |
|
T13 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T5 |
12 |
|
T380 |
1 |
|
T219 |
1 |
| others[1] |
249 |
1 |
|
T5 |
10 |
|
T289 |
1 |
|
T380 |
1 |
| others[2] |
248 |
1 |
|
T5 |
10 |
|
T383 |
1 |
|
T243 |
1 |
| others[3] |
421 |
1 |
|
T6 |
1 |
|
T5 |
17 |
|
T7 |
2 |
| false |
109 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T31 |
1 |
| true |
5600 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T5 |
7 |
|
T7 |
1 |
|
T31 |
10 |
| others[1] |
228 |
1 |
|
T5 |
4 |
|
T380 |
1 |
|
T31 |
12 |
| others[2] |
208 |
1 |
|
T5 |
11 |
|
T380 |
1 |
|
T31 |
7 |
| others[3] |
387 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T77 |
1 |
| false |
104 |
1 |
|
T5 |
8 |
|
T40 |
1 |
|
T73 |
1 |
| true |
5738 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T5 |
22 |
|
T8 |
10 |
|
T47 |
5 |
| others[1] |
1236 |
1 |
|
T5 |
16 |
|
T8 |
7 |
|
T47 |
8 |
| others[2] |
1259 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T8 |
11 |
| others[3] |
2075 |
1 |
|
T20 |
1 |
|
T5 |
34 |
|
T7 |
3 |
| false |
643 |
1 |
|
T4 |
1 |
|
T5 |
15 |
|
T8 |
9 |
| true |
448 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1225 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T8 |
6 |
| others[1] |
1287 |
1 |
|
T20 |
1 |
|
T5 |
21 |
|
T8 |
9 |
| others[2] |
1218 |
1 |
|
T5 |
16 |
|
T7 |
1 |
|
T8 |
11 |
| others[3] |
2059 |
1 |
|
T4 |
1 |
|
T5 |
35 |
|
T7 |
1 |
| false |
643 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T8 |
5 |
| true |
432 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
124 |
1 |
|
T5 |
5 |
|
T31 |
4 |
|
T207 |
1 |
| others[1] |
98 |
1 |
|
T5 |
1 |
|
T7 |
2 |
|
T31 |
4 |
| others[2] |
104 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T77 |
1 |
| others[3] |
168 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T40 |
1 |
| false |
58 |
1 |
|
T5 |
3 |
|
T380 |
1 |
|
T31 |
2 |
| true |
6312 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T5 |
10 |
|
T133 |
1 |
|
T49 |
1 |
| others[1] |
233 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T5 |
13 |
| others[2] |
247 |
1 |
|
T5 |
6 |
|
T140 |
1 |
|
T138 |
1 |
| others[3] |
396 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T40 |
1 |
| false |
120 |
1 |
|
T5 |
8 |
|
T380 |
1 |
|
T31 |
6 |
| true |
5653 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1031 |
1 |
|
T5 |
16 |
|
T8 |
12 |
|
T47 |
7 |
| others[1] |
1050 |
1 |
|
T4 |
1 |
|
T5 |
20 |
|
T7 |
1 |
| others[2] |
1079 |
1 |
|
T6 |
1 |
|
T5 |
19 |
|
T7 |
1 |
| others[3] |
1774 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T5 |
36 |
| false |
536 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T14 |
1 |
| true |
1394 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T5 |
13 |
|
T267 |
1 |
|
T31 |
11 |
| others[1] |
230 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T40 |
1 |
| others[2] |
232 |
1 |
|
T5 |
12 |
|
T24 |
1 |
|
T219 |
1 |
| others[3] |
397 |
1 |
|
T5 |
16 |
|
T65 |
1 |
|
T230 |
1 |
| false |
106 |
1 |
|
T6 |
1 |
|
T5 |
7 |
|
T289 |
1 |
| true |
5647 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T5 |
6 |
|
T40 |
1 |
|
T267 |
1 |
| others[1] |
219 |
1 |
|
T5 |
13 |
|
T31 |
10 |
|
T124 |
7 |
| others[2] |
243 |
1 |
|
T5 |
7 |
|
T7 |
2 |
|
T31 |
13 |
| others[3] |
364 |
1 |
|
T5 |
21 |
|
T77 |
1 |
|
T140 |
1 |
| false |
116 |
1 |
|
T5 |
4 |
|
T380 |
1 |
|
T31 |
6 |
| true |
5687 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T5 |
18 |
|
T8 |
12 |
|
T47 |
7 |
| others[1] |
1244 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| others[2] |
1255 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T8 |
9 |
| others[3] |
2042 |
1 |
|
T5 |
39 |
|
T7 |
1 |
|
T8 |
17 |
| false |
612 |
1 |
|
T5 |
4 |
|
T7 |
2 |
|
T47 |
3 |
| true |
449 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1342 |
1 |
|
T4 |
1 |
|
T5 |
15 |
|
T7 |
1 |
| others[1] |
1177 |
1 |
|
T5 |
27 |
|
T7 |
1 |
|
T8 |
12 |
| others[2] |
1222 |
1 |
|
T19 |
1 |
|
T5 |
22 |
|
T8 |
10 |
| others[3] |
2046 |
1 |
|
T20 |
1 |
|
T5 |
31 |
|
T7 |
2 |
| false |
649 |
1 |
|
T5 |
6 |
|
T8 |
5 |
|
T47 |
3 |
| true |
428 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T5 |
7 |
|
T7 |
1 |
|
T259 |
1 |
| others[1] |
113 |
1 |
|
T5 |
7 |
|
T380 |
1 |
|
T31 |
2 |
| others[2] |
114 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T380 |
1 |
| others[3] |
179 |
1 |
|
T5 |
7 |
|
T7 |
2 |
|
T77 |
1 |
| false |
69 |
1 |
|
T5 |
2 |
|
T31 |
2 |
|
T124 |
2 |
| true |
6294 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
194 |
1 |
|
T5 |
9 |
|
T25 |
1 |
|
T133 |
1 |
| others[1] |
248 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T31 |
8 |
| others[2] |
233 |
1 |
|
T5 |
6 |
|
T73 |
1 |
|
T31 |
7 |
| others[3] |
412 |
1 |
|
T1 |
1 |
|
T5 |
15 |
|
T40 |
1 |
| false |
145 |
1 |
|
T5 |
6 |
|
T31 |
7 |
|
T124 |
7 |
| true |
5632 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1033 |
1 |
|
T4 |
1 |
|
T5 |
24 |
|
T8 |
8 |
| others[1] |
1029 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T5 |
16 |
| others[2] |
1093 |
1 |
|
T5 |
16 |
|
T8 |
9 |
|
T47 |
8 |
| others[3] |
1793 |
1 |
|
T20 |
1 |
|
T5 |
32 |
|
T7 |
1 |
| false |
540 |
1 |
|
T5 |
13 |
|
T8 |
5 |
|
T47 |
1 |
| true |
1376 |
1 |
|
T6 |
1 |
|
T13 |
1 |
|
T14 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |