Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T5 |
9 |
|
T219 |
1 |
|
T31 |
13 |
| others[1] |
253 |
1 |
|
T5 |
3 |
|
T243 |
1 |
|
T380 |
1 |
| others[2] |
220 |
1 |
|
T5 |
11 |
|
T73 |
1 |
|
T77 |
1 |
| others[3] |
394 |
1 |
|
T1 |
1 |
|
T5 |
19 |
|
T7 |
3 |
| false |
111 |
1 |
|
T6 |
1 |
|
T5 |
5 |
|
T31 |
4 |
| true |
5643 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T5 |
13 |
|
T77 |
1 |
|
T31 |
12 |
| others[1] |
200 |
1 |
|
T5 |
14 |
|
T31 |
4 |
|
T124 |
12 |
| others[2] |
229 |
1 |
|
T5 |
13 |
|
T31 |
12 |
|
T207 |
1 |
| others[3] |
372 |
1 |
|
T5 |
15 |
|
T380 |
1 |
|
T382 |
1 |
| false |
128 |
1 |
|
T5 |
6 |
|
T40 |
1 |
|
T73 |
1 |
| true |
5710 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T5 |
20 |
|
T7 |
1 |
|
T8 |
5 |
| others[1] |
1265 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T8 |
15 |
| others[2] |
1272 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T7 |
1 |
| others[3] |
2010 |
1 |
|
T5 |
34 |
|
T7 |
1 |
|
T8 |
15 |
| false |
667 |
1 |
|
T20 |
1 |
|
T5 |
14 |
|
T8 |
4 |
| true |
430 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1284 |
1 |
|
T5 |
25 |
|
T8 |
10 |
|
T47 |
8 |
| others[1] |
1229 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T8 |
14 |
| others[2] |
1208 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T8 |
8 |
| others[3] |
2105 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
43 |
| false |
619 |
1 |
|
T5 |
9 |
|
T8 |
9 |
|
T47 |
4 |
| true |
419 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T383 |
1 |
| others[1] |
106 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T77 |
1 |
| others[2] |
100 |
1 |
|
T5 |
4 |
|
T385 |
1 |
|
T207 |
1 |
| others[3] |
163 |
1 |
|
T5 |
5 |
|
T7 |
2 |
|
T380 |
1 |
| false |
44 |
1 |
|
T5 |
1 |
|
T31 |
1 |
|
T387 |
1 |
| true |
6341 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T5 |
11 |
|
T65 |
1 |
|
T120 |
1 |
| others[1] |
258 |
1 |
|
T5 |
7 |
|
T40 |
1 |
|
T77 |
1 |
| others[2] |
255 |
1 |
|
T5 |
10 |
|
T119 |
1 |
|
T380 |
1 |
| others[3] |
398 |
1 |
|
T5 |
17 |
|
T140 |
1 |
|
T26 |
1 |
| false |
134 |
1 |
|
T5 |
7 |
|
T7 |
1 |
|
T31 |
6 |
| true |
5595 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T5 |
19 |
| others[1] |
1117 |
1 |
|
T20 |
1 |
|
T5 |
30 |
|
T8 |
7 |
| others[2] |
1073 |
1 |
|
T5 |
17 |
|
T7 |
2 |
|
T8 |
10 |
| others[3] |
1747 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T5 |
24 |
| false |
540 |
1 |
|
T5 |
11 |
|
T8 |
5 |
|
T33 |
1 |
| true |
1343 |
1 |
|
T13 |
1 |
|
T14 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T5 |
10 |
|
T7 |
3 |
|
T24 |
1 |
| others[1] |
214 |
1 |
|
T5 |
9 |
|
T31 |
7 |
|
T124 |
17 |
| others[2] |
214 |
1 |
|
T5 |
10 |
|
T32 |
1 |
|
T73 |
1 |
| others[3] |
428 |
1 |
|
T1 |
1 |
|
T5 |
27 |
|
T49 |
1 |
| false |
111 |
1 |
|
T5 |
5 |
|
T140 |
1 |
|
T267 |
1 |
| true |
5658 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
197 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T31 |
12 |
| others[1] |
235 |
1 |
|
T5 |
6 |
|
T73 |
1 |
|
T31 |
13 |
| others[2] |
227 |
1 |
|
T5 |
15 |
|
T40 |
1 |
|
T31 |
14 |
| others[3] |
374 |
1 |
|
T5 |
19 |
|
T7 |
1 |
|
T140 |
1 |
| false |
118 |
1 |
|
T5 |
5 |
|
T31 |
5 |
|
T124 |
2 |
| true |
5713 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1255 |
1 |
|
T20 |
1 |
|
T5 |
19 |
|
T8 |
10 |
| others[1] |
1266 |
1 |
|
T4 |
1 |
|
T5 |
18 |
|
T8 |
10 |
| others[2] |
1219 |
1 |
|
T5 |
23 |
|
T7 |
1 |
|
T8 |
14 |
| others[3] |
2044 |
1 |
|
T5 |
28 |
|
T7 |
2 |
|
T8 |
13 |
| false |
647 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T8 |
3 |
| true |
433 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1292 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
17 |
| others[1] |
1222 |
1 |
|
T5 |
20 |
|
T8 |
8 |
|
T47 |
4 |
| others[2] |
1231 |
1 |
|
T5 |
24 |
|
T7 |
1 |
|
T8 |
6 |
| others[3] |
2032 |
1 |
|
T5 |
34 |
|
T7 |
2 |
|
T8 |
20 |
| false |
657 |
1 |
|
T20 |
1 |
|
T5 |
6 |
|
T8 |
4 |
| true |
430 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T5 |
4 |
|
T380 |
2 |
|
T31 |
1 |
| others[1] |
91 |
1 |
|
T7 |
1 |
|
T31 |
4 |
|
T385 |
1 |
| others[2] |
87 |
1 |
|
T5 |
3 |
|
T7 |
2 |
|
T31 |
1 |
| others[3] |
160 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T77 |
1 |
| false |
55 |
1 |
|
T5 |
4 |
|
T31 |
2 |
|
T62 |
1 |
| true |
6362 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
263 |
1 |
|
T5 |
11 |
|
T31 |
12 |
|
T124 |
16 |
| others[1] |
233 |
1 |
|
T5 |
15 |
|
T7 |
1 |
|
T77 |
1 |
| others[2] |
238 |
1 |
|
T5 |
7 |
|
T25 |
1 |
|
T133 |
1 |
| others[3] |
390 |
1 |
|
T6 |
1 |
|
T5 |
23 |
|
T7 |
1 |
| false |
123 |
1 |
|
T5 |
10 |
|
T73 |
1 |
|
T386 |
1 |
| true |
5617 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T20 |
1 |
|
T5 |
17 |
|
T13 |
1 |
| others[1] |
1014 |
1 |
|
T4 |
1 |
|
T5 |
17 |
|
T8 |
10 |
| others[2] |
1049 |
1 |
|
T5 |
25 |
|
T7 |
1 |
|
T8 |
12 |
| others[3] |
1748 |
1 |
|
T19 |
1 |
|
T5 |
38 |
|
T7 |
3 |
| false |
535 |
1 |
|
T1 |
1 |
|
T5 |
4 |
|
T8 |
5 |
| true |
1440 |
1 |
|
T6 |
1 |
|
T14 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T5 |
4 |
|
T73 |
1 |
|
T31 |
7 |
| others[1] |
222 |
1 |
|
T5 |
12 |
|
T40 |
1 |
|
T289 |
1 |
| others[2] |
213 |
1 |
|
T5 |
12 |
|
T65 |
1 |
|
T230 |
1 |
| others[3] |
383 |
1 |
|
T5 |
15 |
|
T7 |
1 |
|
T32 |
1 |
| false |
105 |
1 |
|
T5 |
4 |
|
T31 |
4 |
|
T50 |
1 |
| true |
5687 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T5 |
8 |
|
T73 |
1 |
|
T380 |
1 |
| others[1] |
231 |
1 |
|
T5 |
11 |
|
T77 |
1 |
|
T380 |
1 |
| others[2] |
220 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T267 |
1 |
| others[3] |
354 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T140 |
1 |
| false |
96 |
1 |
|
T5 |
3 |
|
T382 |
1 |
|
T31 |
2 |
| true |
5746 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1194 |
1 |
|
T5 |
19 |
|
T7 |
1 |
|
T8 |
11 |
| others[1] |
1278 |
1 |
|
T4 |
1 |
|
T5 |
13 |
|
T8 |
11 |
| others[2] |
1220 |
1 |
|
T20 |
1 |
|
T5 |
13 |
|
T8 |
11 |
| others[3] |
2057 |
1 |
|
T19 |
1 |
|
T5 |
44 |
|
T7 |
2 |
| false |
676 |
1 |
|
T5 |
12 |
|
T7 |
1 |
|
T8 |
3 |
| true |
439 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T5 |
20 |
|
T7 |
2 |
|
T8 |
14 |
| others[1] |
1217 |
1 |
|
T1 |
1 |
|
T5 |
19 |
|
T7 |
2 |
| others[2] |
1259 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
18 |
| others[3] |
2063 |
1 |
|
T5 |
32 |
|
T8 |
15 |
|
T47 |
8 |
| false |
641 |
1 |
|
T5 |
12 |
|
T8 |
3 |
|
T33 |
1 |
| true |
425 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T5 |
6 |
|
T380 |
1 |
|
T31 |
6 |
| others[1] |
120 |
1 |
|
T5 |
4 |
|
T383 |
1 |
|
T31 |
5 |
| others[2] |
100 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T77 |
1 |
| others[3] |
155 |
1 |
|
T5 |
3 |
|
T7 |
3 |
|
T380 |
1 |
| false |
57 |
1 |
|
T5 |
1 |
|
T31 |
4 |
|
T385 |
1 |
| true |
6319 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T5 |
13 |
|
T73 |
1 |
|
T31 |
10 |
| others[1] |
241 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T386 |
1 |
| others[2] |
256 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T65 |
1 |
| others[3] |
375 |
1 |
|
T1 |
1 |
|
T5 |
14 |
|
T7 |
1 |
| false |
122 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T140 |
1 |
| true |
5616 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1075 |
1 |
|
T5 |
21 |
|
T8 |
11 |
|
T47 |
7 |
| others[1] |
1064 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
21 |
| others[2] |
1051 |
1 |
|
T20 |
1 |
|
T5 |
24 |
|
T7 |
1 |
| others[3] |
1737 |
1 |
|
T5 |
29 |
|
T7 |
1 |
|
T8 |
20 |
| false |
557 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T8 |
10 |
| true |
1380 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T5 |
7 |
|
T7 |
1 |
|
T49 |
1 |
| others[1] |
220 |
1 |
|
T5 |
9 |
|
T73 |
1 |
|
T289 |
1 |
| others[2] |
243 |
1 |
|
T1 |
1 |
|
T5 |
9 |
|
T138 |
1 |
| others[3] |
418 |
1 |
|
T6 |
1 |
|
T5 |
15 |
|
T40 |
1 |
| false |
109 |
1 |
|
T5 |
6 |
|
T31 |
4 |
|
T385 |
1 |
| true |
5630 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T73 |
1 |
| others[1] |
219 |
1 |
|
T5 |
8 |
|
T31 |
9 |
|
T385 |
1 |
| others[2] |
215 |
1 |
|
T5 |
12 |
|
T31 |
8 |
|
T61 |
1 |
| others[3] |
367 |
1 |
|
T5 |
19 |
|
T40 |
1 |
|
T140 |
1 |
| false |
108 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T31 |
5 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T8 |
9 |
| others[1] |
1248 |
1 |
|
T20 |
1 |
|
T5 |
20 |
|
T8 |
10 |
| others[2] |
1175 |
1 |
|
T5 |
19 |
|
T8 |
14 |
|
T47 |
6 |
| others[3] |
2067 |
1 |
|
T4 |
1 |
|
T5 |
38 |
|
T7 |
2 |
| false |
700 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T8 |
7 |
| true |
452 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1269 |
1 |
|
T5 |
20 |
|
T8 |
5 |
|
T33 |
1 |
| others[1] |
1197 |
1 |
|
T4 |
1 |
|
T5 |
22 |
|
T13 |
1 |
| others[2] |
1243 |
1 |
|
T5 |
13 |
|
T7 |
2 |
|
T8 |
11 |
| others[3] |
2059 |
1 |
|
T20 |
1 |
|
T5 |
39 |
|
T7 |
2 |
| false |
677 |
1 |
|
T5 |
7 |
|
T8 |
5 |
|
T47 |
3 |
| true |
419 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T5 |
5 |
|
T383 |
1 |
|
T380 |
1 |
| others[1] |
117 |
1 |
|
T5 |
8 |
|
T7 |
2 |
|
T31 |
5 |
| others[2] |
97 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T380 |
1 |
| others[3] |
163 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T77 |
1 |
| false |
63 |
1 |
|
T5 |
3 |
|
T31 |
1 |
|
T207 |
1 |
| true |
6330 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T24 |
1 |
| others[1] |
247 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T40 |
1 |
| others[2] |
245 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T26 |
1 |
| others[3] |
382 |
1 |
|
T5 |
14 |
|
T73 |
1 |
|
T77 |
1 |
| false |
121 |
1 |
|
T5 |
3 |
|
T120 |
1 |
|
T31 |
3 |
| true |
5622 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T5 |
22 |
|
T8 |
2 |
|
T33 |
1 |
| others[1] |
999 |
1 |
|
T19 |
1 |
|
T5 |
21 |
|
T8 |
12 |
| others[2] |
1040 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T5 |
18 |
| others[3] |
1765 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
27 |
| false |
589 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T8 |
3 |
| true |
1408 |
1 |
|
T14 |
1 |
|
T24 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T5 |
11 |
|
T383 |
1 |
|
T382 |
1 |
| others[1] |
238 |
1 |
|
T6 |
1 |
|
T5 |
8 |
|
T40 |
1 |
| others[2] |
247 |
1 |
|
T5 |
11 |
|
T65 |
1 |
|
T386 |
1 |
| others[3] |
420 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T34 |
1 |
| false |
124 |
1 |
|
T5 |
4 |
|
T24 |
1 |
|
T243 |
1 |
| true |
5596 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T5 |
7 |
|
T386 |
1 |
|
T383 |
1 |
| others[1] |
209 |
1 |
|
T5 |
5 |
|
T7 |
2 |
|
T31 |
6 |
| others[2] |
222 |
1 |
|
T5 |
13 |
|
T73 |
1 |
|
T382 |
1 |
| others[3] |
397 |
1 |
|
T5 |
18 |
|
T140 |
1 |
|
T380 |
1 |
| false |
130 |
1 |
|
T5 |
7 |
|
T31 |
4 |
|
T124 |
9 |
| true |
5690 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T20 |
1 |
|
T5 |
23 |
|
T7 |
1 |
| others[1] |
1272 |
1 |
|
T5 |
19 |
|
T7 |
1 |
|
T8 |
13 |
| others[2] |
1201 |
1 |
|
T4 |
1 |
|
T5 |
21 |
|
T8 |
9 |
| others[3] |
2052 |
1 |
|
T5 |
34 |
|
T7 |
1 |
|
T8 |
12 |
| false |
655 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T8 |
5 |
| true |
441 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |