Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T5 |
23 |
|
T8 |
10 |
|
T47 |
11 |
| others[1] |
1216 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
23 |
| others[2] |
1258 |
1 |
|
T5 |
22 |
|
T7 |
3 |
|
T8 |
12 |
| others[3] |
2077 |
1 |
|
T5 |
23 |
|
T7 |
1 |
|
T8 |
14 |
| false |
643 |
1 |
|
T5 |
10 |
|
T8 |
7 |
|
T47 |
1 |
| true |
418 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T5 |
4 |
|
T380 |
1 |
|
T31 |
8 |
| others[1] |
100 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T40 |
1 |
| others[2] |
119 |
1 |
|
T5 |
7 |
|
T31 |
2 |
|
T61 |
1 |
| others[3] |
190 |
1 |
|
T5 |
6 |
|
T7 |
2 |
|
T77 |
1 |
| false |
44 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T31 |
1 |
| true |
6310 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T5 |
8 |
|
T26 |
1 |
|
T31 |
15 |
| others[1] |
217 |
1 |
|
T5 |
9 |
|
T32 |
1 |
|
T31 |
5 |
| others[2] |
224 |
1 |
|
T5 |
14 |
|
T138 |
1 |
|
T31 |
4 |
| others[3] |
386 |
1 |
|
T5 |
16 |
|
T386 |
1 |
|
T382 |
1 |
| false |
122 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T77 |
1 |
| true |
5669 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1041 |
1 |
|
T19 |
1 |
|
T5 |
19 |
|
T8 |
13 |
| others[1] |
1095 |
1 |
|
T5 |
21 |
|
T8 |
10 |
|
T47 |
7 |
| others[2] |
971 |
1 |
|
T6 |
1 |
|
T5 |
19 |
|
T7 |
1 |
| others[3] |
1808 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
33 |
| false |
565 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T8 |
5 |
| true |
1384 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T119 |
1 |
| others[1] |
222 |
1 |
|
T5 |
10 |
|
T34 |
1 |
|
T230 |
1 |
| others[2] |
219 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T73 |
1 |
| others[3] |
427 |
1 |
|
T6 |
1 |
|
T5 |
17 |
|
T7 |
1 |
| false |
113 |
1 |
|
T1 |
1 |
|
T5 |
5 |
|
T120 |
1 |
| true |
5660 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T77 |
1 |
| others[1] |
223 |
1 |
|
T5 |
11 |
|
T380 |
1 |
|
T31 |
7 |
| others[2] |
223 |
1 |
|
T5 |
13 |
|
T31 |
7 |
|
T50 |
1 |
| others[3] |
365 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T31 |
20 |
| false |
122 |
1 |
|
T5 |
6 |
|
T31 |
4 |
|
T259 |
1 |
| true |
5722 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1279 |
1 |
|
T19 |
1 |
|
T5 |
22 |
|
T7 |
1 |
| others[1] |
1257 |
1 |
|
T4 |
1 |
|
T5 |
13 |
|
T7 |
1 |
| others[2] |
1225 |
1 |
|
T20 |
1 |
|
T5 |
25 |
|
T8 |
16 |
| others[3] |
2040 |
1 |
|
T5 |
30 |
|
T7 |
1 |
|
T8 |
10 |
| false |
608 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T8 |
5 |
| true |
455 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1188 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T8 |
9 |
| others[1] |
1269 |
1 |
|
T4 |
1 |
|
T5 |
23 |
|
T8 |
10 |
| others[2] |
1263 |
1 |
|
T5 |
20 |
|
T8 |
10 |
|
T47 |
7 |
| others[3] |
2139 |
1 |
|
T20 |
1 |
|
T5 |
31 |
|
T7 |
2 |
| false |
577 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T8 |
4 |
| true |
428 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T380 |
1 |
| others[1] |
103 |
1 |
|
T5 |
3 |
|
T40 |
1 |
|
T77 |
1 |
| others[2] |
110 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T31 |
7 |
| others[3] |
170 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T31 |
8 |
| false |
58 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T124 |
1 |
| true |
6320 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T5 |
12 |
|
T7 |
2 |
|
T24 |
1 |
| others[1] |
213 |
1 |
|
T6 |
1 |
|
T5 |
8 |
|
T219 |
1 |
| others[2] |
229 |
1 |
|
T5 |
7 |
|
T65 |
1 |
|
T140 |
1 |
| others[3] |
408 |
1 |
|
T5 |
12 |
|
T73 |
1 |
|
T138 |
1 |
| false |
139 |
1 |
|
T5 |
3 |
|
T40 |
1 |
|
T77 |
1 |
| true |
5647 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1026 |
1 |
|
T19 |
1 |
|
T5 |
24 |
|
T13 |
1 |
| others[1] |
971 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T8 |
7 |
| others[2] |
1096 |
1 |
|
T6 |
1 |
|
T5 |
21 |
|
T7 |
2 |
| others[3] |
1805 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
32 |
| false |
579 |
1 |
|
T5 |
7 |
|
T8 |
4 |
|
T47 |
3 |
| true |
1387 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T5 |
12 |
|
T267 |
1 |
|
T31 |
9 |
| others[1] |
260 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T65 |
1 |
| others[2] |
235 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T133 |
1 |
| others[3] |
373 |
1 |
|
T1 |
1 |
|
T5 |
11 |
|
T7 |
1 |
| false |
117 |
1 |
|
T5 |
7 |
|
T140 |
1 |
|
T380 |
1 |
| true |
5645 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T5 |
11 |
|
T31 |
6 |
|
T124 |
9 |
| others[1] |
217 |
1 |
|
T5 |
8 |
|
T40 |
1 |
|
T31 |
11 |
| others[2] |
213 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T140 |
1 |
| others[3] |
343 |
1 |
|
T5 |
15 |
|
T73 |
1 |
|
T386 |
1 |
| false |
118 |
1 |
|
T5 |
5 |
|
T31 |
4 |
|
T259 |
2 |
| true |
5745 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T5 |
18 |
|
T7 |
2 |
|
T8 |
10 |
| others[1] |
1272 |
1 |
|
T4 |
1 |
|
T5 |
17 |
|
T7 |
1 |
| others[2] |
1225 |
1 |
|
T20 |
1 |
|
T5 |
24 |
|
T8 |
10 |
| others[3] |
1993 |
1 |
|
T5 |
29 |
|
T7 |
1 |
|
T8 |
20 |
| false |
664 |
1 |
|
T5 |
13 |
|
T8 |
3 |
|
T33 |
1 |
| true |
449 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T5 |
15 |
|
T7 |
1 |
|
T8 |
5 |
| others[1] |
1248 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
18 |
| others[2] |
1262 |
1 |
|
T5 |
24 |
|
T8 |
8 |
|
T47 |
6 |
| others[3] |
2046 |
1 |
|
T5 |
37 |
|
T7 |
2 |
|
T13 |
1 |
| false |
632 |
1 |
|
T5 |
7 |
|
T8 |
7 |
|
T47 |
2 |
| true |
417 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T77 |
1 |
| others[1] |
113 |
1 |
|
T5 |
4 |
|
T380 |
1 |
|
T31 |
1 |
| others[2] |
100 |
1 |
|
T5 |
5 |
|
T383 |
1 |
|
T31 |
2 |
| others[3] |
195 |
1 |
|
T5 |
9 |
|
T7 |
2 |
|
T267 |
1 |
| false |
50 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T73 |
1 |
| true |
6308 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T230 |
1 |
| others[1] |
226 |
1 |
|
T5 |
11 |
|
T40 |
1 |
|
T133 |
1 |
| others[2] |
264 |
1 |
|
T5 |
12 |
|
T383 |
1 |
|
T31 |
7 |
| others[3] |
397 |
1 |
|
T5 |
17 |
|
T24 |
1 |
|
T32 |
1 |
| false |
114 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T31 |
5 |
| true |
5637 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1029 |
1 |
|
T5 |
20 |
|
T7 |
2 |
|
T8 |
11 |
| others[1] |
1075 |
1 |
|
T5 |
24 |
|
T7 |
1 |
|
T14 |
1 |
| others[2] |
1103 |
1 |
|
T5 |
19 |
|
T7 |
1 |
|
T13 |
1 |
| others[3] |
1747 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T5 |
31 |
| false |
555 |
1 |
|
T4 |
1 |
|
T5 |
7 |
|
T8 |
7 |
| true |
1355 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T5 |
13 |
| others[1] |
230 |
1 |
|
T5 |
9 |
|
T140 |
1 |
|
T383 |
1 |
| others[2] |
224 |
1 |
|
T5 |
12 |
|
T289 |
1 |
|
T49 |
1 |
| others[3] |
376 |
1 |
|
T5 |
15 |
|
T24 |
1 |
|
T32 |
1 |
| false |
119 |
1 |
|
T5 |
7 |
|
T65 |
1 |
|
T77 |
1 |
| true |
5683 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T5 |
11 |
|
T140 |
1 |
|
T31 |
8 |
| others[1] |
201 |
1 |
|
T5 |
6 |
|
T380 |
1 |
|
T31 |
14 |
| others[2] |
238 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T31 |
11 |
| others[3] |
376 |
1 |
|
T5 |
15 |
|
T7 |
1 |
|
T73 |
1 |
| false |
106 |
1 |
|
T5 |
4 |
|
T31 |
5 |
|
T207 |
1 |
| true |
5739 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T5 |
16 |
|
T7 |
1 |
|
T8 |
10 |
| others[1] |
1248 |
1 |
|
T5 |
22 |
|
T7 |
1 |
|
T8 |
13 |
| others[2] |
1293 |
1 |
|
T20 |
1 |
|
T5 |
19 |
|
T7 |
1 |
| others[3] |
2011 |
1 |
|
T4 |
1 |
|
T5 |
33 |
|
T7 |
1 |
| false |
644 |
1 |
|
T5 |
11 |
|
T8 |
4 |
|
T47 |
6 |
| true |
433 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T5 |
16 |
|
T8 |
8 |
|
T47 |
4 |
| others[1] |
1212 |
1 |
|
T5 |
22 |
|
T7 |
1 |
|
T8 |
7 |
| others[2] |
1286 |
1 |
|
T20 |
1 |
|
T5 |
19 |
|
T7 |
1 |
| others[3] |
2066 |
1 |
|
T4 |
1 |
|
T5 |
35 |
|
T7 |
2 |
| false |
646 |
1 |
|
T5 |
9 |
|
T8 |
3 |
|
T33 |
1 |
| true |
424 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
124 |
1 |
|
T5 |
1 |
|
T383 |
1 |
|
T31 |
6 |
| others[1] |
114 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T31 |
8 |
| others[2] |
120 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T31 |
9 |
| others[3] |
181 |
1 |
|
T5 |
2 |
|
T7 |
1 |
|
T73 |
1 |
| false |
59 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T380 |
1 |
| true |
6266 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T133 |
1 |
| others[1] |
242 |
1 |
|
T5 |
9 |
|
T267 |
1 |
|
T120 |
1 |
| others[2] |
194 |
1 |
|
T5 |
9 |
|
T40 |
1 |
|
T382 |
1 |
| others[3] |
405 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T26 |
1 |
| false |
115 |
1 |
|
T5 |
6 |
|
T32 |
1 |
|
T31 |
4 |
| true |
5669 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1085 |
1 |
|
T5 |
21 |
|
T7 |
2 |
|
T8 |
9 |
| others[1] |
1044 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T5 |
18 |
| others[2] |
997 |
1 |
|
T1 |
1 |
|
T5 |
20 |
|
T7 |
1 |
| others[3] |
1817 |
1 |
|
T6 |
1 |
|
T20 |
1 |
|
T5 |
34 |
| false |
550 |
1 |
|
T5 |
8 |
|
T8 |
5 |
|
T47 |
4 |
| true |
1371 |
1 |
|
T13 |
1 |
|
T14 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T5 |
12 |
|
T73 |
1 |
|
T133 |
1 |
| others[1] |
235 |
1 |
|
T5 |
18 |
|
T230 |
1 |
|
T31 |
5 |
| others[2] |
243 |
1 |
|
T1 |
1 |
|
T5 |
13 |
|
T7 |
1 |
| others[3] |
387 |
1 |
|
T5 |
16 |
|
T7 |
1 |
|
T24 |
1 |
| false |
133 |
1 |
|
T6 |
1 |
|
T5 |
4 |
|
T140 |
1 |
| true |
5655 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T77 |
1 |
| others[1] |
215 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T382 |
1 |
| others[2] |
232 |
1 |
|
T5 |
7 |
|
T31 |
12 |
|
T259 |
1 |
| others[3] |
352 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T40 |
1 |
| false |
104 |
1 |
|
T5 |
5 |
|
T31 |
4 |
|
T124 |
6 |
| true |
5728 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1286 |
1 |
|
T5 |
21 |
|
T8 |
16 |
|
T47 |
12 |
| others[1] |
1211 |
1 |
|
T5 |
26 |
|
T8 |
11 |
|
T47 |
3 |
| others[2] |
1206 |
1 |
|
T20 |
1 |
|
T5 |
12 |
|
T7 |
1 |
| others[3] |
2075 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
36 |
| false |
657 |
1 |
|
T5 |
6 |
|
T8 |
4 |
|
T47 |
3 |
| true |
429 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T42 |
1 |
|
T167 |
1 |
|
T87 |
1 |
| others[1] |
12 |
1 |
|
T388 |
1 |
|
T389 |
1 |
|
T390 |
1 |
| others[2] |
8 |
1 |
|
T117 |
1 |
|
T165 |
1 |
|
T391 |
1 |
| others[3] |
15 |
1 |
|
T83 |
1 |
|
T174 |
1 |
|
T392 |
1 |
| false |
4 |
1 |
|
T393 |
1 |
|
T394 |
1 |
|
T395 |
1 |
| true |
45 |
1 |
|
T12 |
1 |
|
T55 |
1 |
|
T167 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T396 |
1 |
|
T397 |
1 |
|
T398 |
1 |
| others[1] |
4 |
1 |
|
T23 |
1 |
|
T399 |
1 |
|
T400 |
1 |
| others[2] |
2 |
1 |
|
T401 |
1 |
|
T402 |
1 |
|
- |
- |
| others[3] |
6 |
1 |
|
T403 |
1 |
|
T404 |
1 |
|
T405 |
1 |
| false |
9 |
1 |
|
T184 |
1 |
|
T185 |
1 |
|
T406 |
1 |
| true |
21 |
1 |
|
T30 |
1 |
|
T407 |
1 |
|
T408 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T409 |
1 |
|
T410 |
1 |
|
T411 |
1 |
| others[1] |
5 |
1 |
|
T23 |
1 |
|
T405 |
1 |
|
T412 |
1 |
| others[2] |
5 |
1 |
|
T30 |
1 |
|
T185 |
1 |
|
T413 |
1 |
| others[3] |
2 |
1 |
|
T396 |
1 |
|
T414 |
1 |
|
- |
- |
| false |
9 |
1 |
|
T404 |
1 |
|
T397 |
1 |
|
T401 |
1 |
| true |
20 |
1 |
|
T184 |
1 |
|
T403 |
1 |
|
T407 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |