Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10128 |
1 |
|
T12 |
2 |
|
T5 |
19 |
|
T7 |
2 |
| others[1] |
818 |
1 |
|
T5 |
18 |
|
T7 |
1 |
|
T8 |
12 |
| others[2] |
786 |
1 |
|
T4 |
1 |
|
T5 |
14 |
|
T7 |
1 |
| others[3] |
1275 |
1 |
|
T20 |
1 |
|
T5 |
42 |
|
T8 |
11 |
| false |
403 |
1 |
|
T5 |
8 |
|
T8 |
4 |
|
T47 |
3 |
| true |
523 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2291 |
1 |
|
T12 |
1 |
|
T5 |
9 |
|
T8 |
12 |
| others[1] |
2371 |
1 |
|
T12 |
1 |
|
T5 |
6 |
|
T7 |
1 |
| others[2] |
2381 |
1 |
|
T5 |
11 |
|
T7 |
2 |
|
T8 |
12 |
| others[3] |
3962 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
12 |
| false |
1314 |
1 |
|
T5 |
2 |
|
T8 |
9 |
|
T21 |
26 |
| true |
1614 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9563 |
1 |
|
T1 |
1 |
|
T12 |
2 |
|
T6 |
1 |
| others[1] |
262 |
1 |
|
T5 |
8 |
|
T215 |
1 |
|
T64 |
1 |
| others[2] |
277 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T40 |
1 |
| others[3] |
442 |
1 |
|
T20 |
1 |
|
T5 |
15 |
|
T41 |
1 |
| false |
134 |
1 |
|
T5 |
6 |
|
T114 |
1 |
|
T230 |
1 |
| true |
3255 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T5 |
52 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9821 |
1 |
|
T12 |
2 |
|
T5 |
13 |
|
T7 |
2 |
| others[1] |
415 |
1 |
|
T5 |
7 |
|
T8 |
1 |
|
T47 |
1 |
| others[2] |
482 |
1 |
|
T1 |
1 |
|
T5 |
8 |
|
T7 |
1 |
| others[3] |
773 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T5 |
12 |
| false |
237 |
1 |
|
T5 |
4 |
|
T8 |
3 |
|
T22 |
1 |
| true |
2205 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
57 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9530 |
1 |
|
T12 |
2 |
|
T5 |
6 |
|
T7 |
2 |
| others[1] |
250 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T81 |
1 |
| others[2] |
247 |
1 |
|
T5 |
8 |
|
T189 |
1 |
|
T190 |
1 |
| others[3] |
406 |
1 |
|
T5 |
19 |
|
T24 |
1 |
|
T74 |
1 |
| false |
141 |
1 |
|
T5 |
5 |
|
T33 |
1 |
|
T234 |
1 |
| true |
3359 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9509 |
1 |
|
T12 |
2 |
|
T5 |
12 |
|
T21 |
215 |
| others[1] |
254 |
1 |
|
T5 |
9 |
|
T73 |
1 |
|
T27 |
1 |
| others[2] |
273 |
1 |
|
T20 |
1 |
|
T5 |
14 |
|
T113 |
1 |
| others[3] |
399 |
1 |
|
T5 |
12 |
|
T7 |
1 |
|
T22 |
1 |
| false |
122 |
1 |
|
T5 |
3 |
|
T31 |
3 |
|
T61 |
1 |
| true |
3376 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10145 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T5 |
20 |
| others[1] |
780 |
1 |
|
T5 |
25 |
|
T7 |
1 |
|
T8 |
10 |
| others[2] |
812 |
1 |
|
T5 |
17 |
|
T8 |
7 |
|
T47 |
6 |
| others[3] |
1305 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T5 |
27 |
| false |
411 |
1 |
|
T19 |
1 |
|
T5 |
12 |
|
T8 |
5 |
| true |
480 |
1 |
|
T6 |
1 |
|
T7 |
2 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10096 |
1 |
|
T12 |
2 |
|
T5 |
15 |
|
T8 |
5 |
| others[1] |
774 |
1 |
|
T5 |
21 |
|
T8 |
6 |
|
T47 |
1 |
| others[2] |
797 |
1 |
|
T4 |
1 |
|
T5 |
20 |
|
T8 |
12 |
| others[3] |
1313 |
1 |
|
T20 |
1 |
|
T5 |
38 |
|
T7 |
1 |
| false |
407 |
1 |
|
T5 |
7 |
|
T8 |
10 |
|
T47 |
3 |
| true |
513 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2424 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T8 |
10 |
| others[1] |
2394 |
1 |
|
T5 |
7 |
|
T8 |
10 |
|
T21 |
47 |
| others[2] |
2349 |
1 |
|
T20 |
1 |
|
T5 |
13 |
|
T7 |
1 |
| others[3] |
3925 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T5 |
17 |
| false |
1248 |
1 |
|
T5 |
2 |
|
T7 |
2 |
|
T8 |
6 |
| true |
1560 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9531 |
1 |
|
T12 |
2 |
|
T5 |
12 |
|
T21 |
215 |
| others[1] |
301 |
1 |
|
T5 |
8 |
|
T24 |
1 |
|
T22 |
1 |
| others[2] |
277 |
1 |
|
T6 |
1 |
|
T5 |
11 |
|
T7 |
1 |
| others[3] |
460 |
1 |
|
T20 |
1 |
|
T5 |
18 |
|
T189 |
1 |
| false |
150 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T118 |
2 |
| true |
3181 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9758 |
1 |
|
T12 |
2 |
|
T5 |
10 |
|
T8 |
4 |
| others[1] |
461 |
1 |
|
T5 |
9 |
|
T7 |
1 |
|
T8 |
9 |
| others[2] |
451 |
1 |
|
T5 |
13 |
|
T7 |
2 |
|
T8 |
6 |
| others[3] |
843 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T20 |
1 |
| false |
223 |
1 |
|
T5 |
7 |
|
T8 |
3 |
|
T156 |
1 |
| true |
2164 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9533 |
1 |
|
T1 |
1 |
|
T12 |
2 |
|
T5 |
8 |
| others[1] |
276 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T24 |
1 |
| others[2] |
253 |
1 |
|
T5 |
11 |
|
T77 |
1 |
|
T113 |
1 |
| others[3] |
463 |
1 |
|
T6 |
1 |
|
T5 |
17 |
|
T22 |
1 |
| false |
134 |
1 |
|
T5 |
5 |
|
T31 |
3 |
|
T124 |
7 |
| true |
3241 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9543 |
1 |
|
T12 |
2 |
|
T5 |
12 |
|
T21 |
215 |
| others[1] |
227 |
1 |
|
T5 |
4 |
|
T22 |
1 |
|
T189 |
1 |
| others[2] |
279 |
1 |
|
T5 |
18 |
|
T74 |
1 |
|
T64 |
1 |
| others[3] |
418 |
1 |
|
T5 |
14 |
|
T22 |
1 |
|
T234 |
1 |
| false |
128 |
1 |
|
T5 |
4 |
|
T267 |
1 |
|
T118 |
1 |
| true |
3305 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10071 |
1 |
|
T12 |
2 |
|
T5 |
24 |
|
T8 |
10 |
| others[1] |
778 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| others[2] |
772 |
1 |
|
T5 |
20 |
|
T8 |
11 |
|
T47 |
10 |
| others[3] |
1337 |
1 |
|
T5 |
29 |
|
T8 |
20 |
|
T33 |
1 |
| false |
423 |
1 |
|
T5 |
6 |
|
T7 |
1 |
|
T8 |
2 |
| true |
519 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T7 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10103 |
1 |
|
T12 |
2 |
|
T5 |
24 |
|
T8 |
8 |
| others[1] |
816 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T7 |
1 |
| others[2] |
767 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T5 |
11 |
| others[3] |
1262 |
1 |
|
T5 |
38 |
|
T8 |
14 |
|
T47 |
7 |
| false |
427 |
1 |
|
T5 |
12 |
|
T7 |
1 |
|
T8 |
7 |
| true |
525 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2429 |
1 |
|
T12 |
2 |
|
T20 |
1 |
|
T5 |
13 |
| others[1] |
2355 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T7 |
2 |
| others[2] |
2376 |
1 |
|
T5 |
7 |
|
T8 |
11 |
|
T21 |
39 |
| others[3] |
3914 |
1 |
|
T5 |
15 |
|
T7 |
1 |
|
T8 |
14 |
| false |
1268 |
1 |
|
T5 |
3 |
|
T8 |
2 |
|
T21 |
27 |
| true |
1558 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9538 |
1 |
|
T12 |
2 |
|
T5 |
7 |
|
T24 |
1 |
| others[1] |
312 |
1 |
|
T1 |
1 |
|
T5 |
12 |
|
T22 |
1 |
| others[2] |
278 |
1 |
|
T20 |
1 |
|
T5 |
8 |
|
T33 |
1 |
| others[3] |
434 |
1 |
|
T5 |
12 |
|
T7 |
2 |
|
T189 |
1 |
| false |
146 |
1 |
|
T6 |
1 |
|
T5 |
6 |
|
T25 |
1 |
| true |
3192 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T5 |
56 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9774 |
1 |
|
T12 |
2 |
|
T20 |
1 |
|
T5 |
10 |
| others[1] |
460 |
1 |
|
T5 |
14 |
|
T8 |
4 |
|
T47 |
1 |
| others[2] |
466 |
1 |
|
T5 |
6 |
|
T7 |
3 |
|
T13 |
1 |
| others[3] |
751 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T5 |
13 |
| false |
246 |
1 |
|
T5 |
6 |
|
T8 |
4 |
|
T24 |
1 |
| true |
2203 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
52 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9536 |
1 |
|
T12 |
2 |
|
T5 |
8 |
|
T21 |
215 |
| others[1] |
245 |
1 |
|
T5 |
10 |
|
T138 |
1 |
|
T119 |
1 |
| others[2] |
252 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T140 |
1 |
| others[3] |
457 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
20 |
| false |
142 |
1 |
|
T7 |
2 |
|
T74 |
1 |
|
T76 |
1 |
| true |
3268 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9532 |
1 |
|
T12 |
2 |
|
T5 |
16 |
|
T21 |
215 |
| others[1] |
242 |
1 |
|
T5 |
12 |
|
T7 |
1 |
|
T189 |
1 |
| others[2] |
240 |
1 |
|
T5 |
10 |
|
T33 |
1 |
|
T22 |
1 |
| others[3] |
427 |
1 |
|
T20 |
1 |
|
T5 |
12 |
|
T7 |
1 |
| false |
155 |
1 |
|
T5 |
3 |
|
T31 |
4 |
|
T415 |
1 |
| true |
3304 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10063 |
1 |
|
T12 |
2 |
|
T20 |
1 |
|
T5 |
19 |
| others[1] |
783 |
1 |
|
T5 |
17 |
|
T7 |
1 |
|
T8 |
10 |
| others[2] |
763 |
1 |
|
T5 |
22 |
|
T7 |
1 |
|
T13 |
1 |
| others[3] |
1338 |
1 |
|
T4 |
1 |
|
T5 |
29 |
|
T8 |
17 |
| false |
446 |
1 |
|
T5 |
14 |
|
T8 |
4 |
|
T47 |
3 |
| true |
507 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10056 |
1 |
|
T12 |
2 |
|
T5 |
28 |
|
T7 |
1 |
| others[1] |
811 |
1 |
|
T5 |
23 |
|
T7 |
1 |
|
T8 |
11 |
| others[2] |
779 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
11 |
| others[3] |
1312 |
1 |
|
T5 |
32 |
|
T8 |
13 |
|
T33 |
1 |
| false |
420 |
1 |
|
T5 |
7 |
|
T8 |
9 |
|
T47 |
5 |
| true |
522 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2401 |
1 |
|
T12 |
1 |
|
T5 |
8 |
|
T7 |
1 |
| others[1] |
2352 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T8 |
10 |
| others[2] |
2415 |
1 |
|
T5 |
3 |
|
T8 |
13 |
|
T21 |
57 |
| others[3] |
3945 |
1 |
|
T20 |
1 |
|
T5 |
16 |
|
T7 |
2 |
| false |
1214 |
1 |
|
T12 |
1 |
|
T5 |
4 |
|
T7 |
1 |
| true |
1573 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9532 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T5 |
9 |
| others[1] |
296 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T5 |
10 |
| others[2] |
258 |
1 |
|
T5 |
5 |
|
T74 |
1 |
|
T118 |
1 |
| others[3] |
467 |
1 |
|
T6 |
1 |
|
T5 |
11 |
|
T7 |
1 |
| false |
126 |
1 |
|
T5 |
7 |
|
T65 |
1 |
|
T234 |
1 |
| true |
3221 |
1 |
|
T19 |
1 |
|
T5 |
59 |
|
T7 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9746 |
1 |
|
T12 |
2 |
|
T5 |
11 |
|
T7 |
1 |
| others[1] |
475 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T13 |
1 |
| others[2] |
449 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T5 |
11 |
| others[3] |
766 |
1 |
|
T19 |
1 |
|
T5 |
16 |
|
T7 |
2 |
| false |
255 |
1 |
|
T1 |
1 |
|
T5 |
9 |
|
T8 |
2 |
| true |
2209 |
1 |
|
T20 |
1 |
|
T5 |
46 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9531 |
1 |
|
T12 |
2 |
|
T6 |
1 |
|
T5 |
12 |
| others[1] |
269 |
1 |
|
T5 |
10 |
|
T33 |
1 |
|
T138 |
1 |
| others[2] |
262 |
1 |
|
T5 |
13 |
|
T32 |
1 |
|
T74 |
1 |
| others[3] |
453 |
1 |
|
T20 |
1 |
|
T5 |
10 |
|
T7 |
1 |
| false |
130 |
1 |
|
T5 |
4 |
|
T140 |
1 |
|
T118 |
1 |
| true |
3255 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9547 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T5 |
9 |
| others[1] |
242 |
1 |
|
T5 |
10 |
|
T22 |
1 |
|
T76 |
1 |
| others[2] |
232 |
1 |
|
T5 |
11 |
|
T144 |
1 |
|
T114 |
1 |
| others[3] |
415 |
1 |
|
T5 |
16 |
|
T7 |
1 |
|
T33 |
1 |
| false |
138 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T118 |
1 |
| true |
3326 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10093 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T20 |
1 |
| others[1] |
763 |
1 |
|
T5 |
13 |
|
T8 |
9 |
|
T33 |
1 |
| others[2] |
794 |
1 |
|
T1 |
1 |
|
T5 |
21 |
|
T8 |
14 |
| others[3] |
1309 |
1 |
|
T5 |
36 |
|
T7 |
2 |
|
T8 |
18 |
| false |
441 |
1 |
|
T5 |
8 |
|
T8 |
5 |
|
T24 |
1 |
| true |
500 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T7 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10072 |
1 |
|
T12 |
2 |
|
T20 |
1 |
|
T5 |
15 |
| others[1] |
821 |
1 |
|
T5 |
24 |
|
T7 |
1 |
|
T8 |
10 |
| others[2] |
777 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T8 |
8 |
| others[3] |
1284 |
1 |
|
T4 |
1 |
|
T5 |
35 |
|
T7 |
1 |
| false |
423 |
1 |
|
T5 |
13 |
|
T8 |
5 |
|
T47 |
2 |
| true |
523 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2395 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T8 |
7 |
| others[1] |
2374 |
1 |
|
T5 |
5 |
|
T7 |
1 |
|
T8 |
7 |
| others[2] |
2354 |
1 |
|
T12 |
1 |
|
T20 |
1 |
|
T5 |
10 |
| others[3] |
3970 |
1 |
|
T4 |
1 |
|
T12 |
1 |
|
T5 |
19 |
| false |
1215 |
1 |
|
T5 |
2 |
|
T8 |
3 |
|
T21 |
16 |
| true |
1592 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9580 |
1 |
|
T12 |
2 |
|
T5 |
10 |
|
T33 |
1 |
| others[1] |
249 |
1 |
|
T1 |
1 |
|
T5 |
8 |
|
T32 |
1 |
| others[2] |
272 |
1 |
|
T5 |
5 |
|
T76 |
1 |
|
T77 |
1 |
| others[3] |
487 |
1 |
|
T4 |
1 |
|
T6 |
1 |
|
T5 |
14 |
| false |
130 |
1 |
|
T5 |
4 |
|
T7 |
1 |
|
T220 |
1 |
| true |
3182 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T5 |
60 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |