Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9779 |
1 |
|
T12 |
2 |
|
T5 |
9 |
|
T7 |
1 |
| others[1] |
447 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T8 |
3 |
| others[2] |
479 |
1 |
|
T5 |
11 |
|
T8 |
8 |
|
T47 |
7 |
| others[3] |
788 |
1 |
|
T5 |
19 |
|
T7 |
2 |
|
T14 |
1 |
| false |
223 |
1 |
|
T4 |
1 |
|
T5 |
4 |
|
T8 |
3 |
| true |
2184 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9506 |
1 |
|
T12 |
2 |
|
T5 |
10 |
|
T21 |
215 |
| others[1] |
264 |
1 |
|
T5 |
9 |
|
T27 |
1 |
|
T138 |
1 |
| others[2] |
264 |
1 |
|
T5 |
18 |
|
T76 |
1 |
|
T113 |
1 |
| others[3] |
448 |
1 |
|
T5 |
16 |
|
T24 |
1 |
|
T40 |
1 |
| false |
144 |
1 |
|
T4 |
1 |
|
T5 |
9 |
|
T7 |
1 |
| true |
3274 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9499 |
1 |
|
T12 |
2 |
|
T5 |
6 |
|
T7 |
2 |
| others[1] |
247 |
1 |
|
T5 |
12 |
|
T22 |
1 |
|
T189 |
1 |
| others[2] |
254 |
1 |
|
T5 |
13 |
|
T33 |
1 |
|
T31 |
13 |
| others[3] |
443 |
1 |
|
T5 |
12 |
|
T7 |
1 |
|
T190 |
1 |
| false |
140 |
1 |
|
T5 |
3 |
|
T31 |
6 |
|
T28 |
1 |
| true |
3317 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10065 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T5 |
21 |
| others[1] |
841 |
1 |
|
T20 |
1 |
|
T5 |
20 |
|
T13 |
1 |
| others[2] |
759 |
1 |
|
T5 |
20 |
|
T8 |
7 |
|
T33 |
1 |
| others[3] |
1334 |
1 |
|
T5 |
30 |
|
T7 |
2 |
|
T8 |
13 |
| false |
386 |
1 |
|
T5 |
10 |
|
T8 |
3 |
|
T47 |
4 |
| true |
515 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10026 |
1 |
|
T12 |
2 |
|
T5 |
19 |
|
T8 |
9 |
| others[1] |
761 |
1 |
|
T5 |
18 |
|
T8 |
12 |
|
T47 |
7 |
| others[2] |
847 |
1 |
|
T20 |
1 |
|
T5 |
17 |
|
T8 |
14 |
| others[3] |
1296 |
1 |
|
T4 |
1 |
|
T5 |
39 |
|
T7 |
1 |
| false |
425 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T8 |
3 |
| true |
545 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2364 |
1 |
|
T4 |
1 |
|
T12 |
1 |
|
T5 |
9 |
| others[1] |
2435 |
1 |
|
T20 |
1 |
|
T5 |
14 |
|
T7 |
2 |
| others[2] |
2348 |
1 |
|
T5 |
10 |
|
T8 |
8 |
|
T21 |
43 |
| others[3] |
3985 |
1 |
|
T12 |
1 |
|
T5 |
13 |
|
T8 |
20 |
| false |
1227 |
1 |
|
T5 |
3 |
|
T7 |
1 |
|
T8 |
9 |
| true |
1541 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9537 |
1 |
|
T12 |
2 |
|
T5 |
8 |
|
T7 |
1 |
| others[1] |
275 |
1 |
|
T5 |
10 |
|
T32 |
1 |
|
T74 |
1 |
| others[2] |
276 |
1 |
|
T5 |
8 |
|
T25 |
1 |
|
T22 |
1 |
| others[3] |
471 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T5 |
16 |
| false |
138 |
1 |
|
T5 |
8 |
|
T31 |
4 |
|
T385 |
1 |
| true |
3203 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9777 |
1 |
|
T12 |
2 |
|
T5 |
8 |
|
T7 |
2 |
| others[1] |
425 |
1 |
|
T5 |
8 |
|
T8 |
5 |
|
T33 |
1 |
| others[2] |
469 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
7 |
| others[3] |
801 |
1 |
|
T5 |
20 |
|
T7 |
2 |
|
T14 |
1 |
| false |
238 |
1 |
|
T5 |
6 |
|
T8 |
2 |
|
T41 |
1 |
| true |
2190 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9531 |
1 |
|
T12 |
2 |
|
T5 |
10 |
|
T21 |
215 |
| others[1] |
249 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T24 |
1 |
| others[2] |
269 |
1 |
|
T4 |
1 |
|
T5 |
9 |
|
T144 |
1 |
| others[3] |
443 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T22 |
1 |
| false |
136 |
1 |
|
T5 |
5 |
|
T342 |
1 |
|
T31 |
4 |
| true |
3272 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9530 |
1 |
|
T12 |
2 |
|
T5 |
9 |
|
T21 |
215 |
| others[1] |
251 |
1 |
|
T5 |
12 |
|
T7 |
1 |
|
T140 |
1 |
| others[2] |
241 |
1 |
|
T5 |
10 |
|
T33 |
1 |
|
T76 |
1 |
| others[3] |
425 |
1 |
|
T20 |
1 |
|
T5 |
17 |
|
T7 |
2 |
| false |
128 |
1 |
|
T4 |
1 |
|
T5 |
4 |
|
T114 |
1 |
| true |
3325 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10095 |
1 |
|
T4 |
1 |
|
T12 |
2 |
|
T5 |
20 |
| others[1] |
780 |
1 |
|
T20 |
1 |
|
T5 |
16 |
|
T7 |
1 |
| others[2] |
809 |
1 |
|
T5 |
17 |
|
T8 |
13 |
|
T47 |
9 |
| others[3] |
1301 |
1 |
|
T5 |
34 |
|
T7 |
1 |
|
T8 |
15 |
| false |
429 |
1 |
|
T5 |
14 |
|
T8 |
3 |
|
T33 |
1 |
| true |
486 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10047 |
1 |
|
T12 |
2 |
|
T5 |
17 |
|
T8 |
7 |
| others[1] |
757 |
1 |
|
T4 |
1 |
|
T5 |
18 |
|
T7 |
1 |
| others[2] |
814 |
1 |
|
T20 |
1 |
|
T5 |
21 |
|
T8 |
9 |
| others[3] |
1344 |
1 |
|
T5 |
35 |
|
T8 |
17 |
|
T33 |
1 |
| false |
408 |
1 |
|
T5 |
10 |
|
T8 |
3 |
|
T47 |
8 |
| true |
530 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2363 |
1 |
|
T20 |
1 |
|
T5 |
3 |
|
T7 |
2 |
| others[1] |
2277 |
1 |
|
T12 |
1 |
|
T5 |
10 |
|
T8 |
10 |
| others[2] |
2447 |
1 |
|
T12 |
1 |
|
T5 |
7 |
|
T8 |
7 |
| others[3] |
3989 |
1 |
|
T5 |
20 |
|
T7 |
2 |
|
T8 |
19 |
| false |
1267 |
1 |
|
T4 |
1 |
|
T5 |
7 |
|
T8 |
8 |
| true |
1557 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9541 |
1 |
|
T12 |
2 |
|
T5 |
9 |
|
T21 |
215 |
| others[1] |
280 |
1 |
|
T4 |
1 |
|
T5 |
11 |
|
T40 |
1 |
| others[2] |
235 |
1 |
|
T6 |
1 |
|
T5 |
7 |
|
T33 |
1 |
| others[3] |
458 |
1 |
|
T5 |
20 |
|
T7 |
1 |
|
T27 |
1 |
| false |
147 |
1 |
|
T5 |
3 |
|
T24 |
1 |
|
T41 |
1 |
| true |
3239 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9763 |
1 |
|
T12 |
2 |
|
T5 |
14 |
|
T7 |
1 |
| others[1] |
478 |
1 |
|
T1 |
1 |
|
T5 |
15 |
|
T8 |
4 |
| others[2] |
443 |
1 |
|
T5 |
8 |
|
T7 |
3 |
|
T8 |
5 |
| others[3] |
760 |
1 |
|
T4 |
1 |
|
T5 |
18 |
|
T8 |
4 |
| false |
231 |
1 |
|
T5 |
4 |
|
T8 |
2 |
|
T47 |
2 |
| true |
2225 |
1 |
|
T19 |
1 |
|
T6 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9545 |
1 |
|
T12 |
2 |
|
T5 |
10 |
|
T7 |
1 |
| others[1] |
257 |
1 |
|
T1 |
1 |
|
T5 |
5 |
|
T7 |
1 |
| others[2] |
249 |
1 |
|
T5 |
8 |
|
T22 |
1 |
|
T215 |
1 |
| others[3] |
405 |
1 |
|
T5 |
17 |
|
T7 |
2 |
|
T189 |
1 |
| false |
140 |
1 |
|
T5 |
6 |
|
T190 |
1 |
|
T230 |
1 |
| true |
3304 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9518 |
1 |
|
T12 |
2 |
|
T5 |
9 |
|
T21 |
215 |
| others[1] |
242 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T22 |
1 |
| others[2] |
228 |
1 |
|
T4 |
1 |
|
T5 |
10 |
|
T22 |
1 |
| others[3] |
436 |
1 |
|
T5 |
18 |
|
T73 |
1 |
|
T77 |
1 |
| false |
126 |
1 |
|
T5 |
3 |
|
T64 |
1 |
|
T31 |
4 |
| true |
3350 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10051 |
1 |
|
T12 |
2 |
|
T5 |
14 |
|
T7 |
1 |
| others[1] |
818 |
1 |
|
T5 |
23 |
|
T7 |
1 |
|
T8 |
8 |
| others[2] |
778 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
15 |
| others[3] |
1339 |
1 |
|
T5 |
37 |
|
T7 |
1 |
|
T8 |
22 |
| false |
422 |
1 |
|
T5 |
12 |
|
T8 |
4 |
|
T33 |
1 |
| true |
492 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10045 |
1 |
|
T12 |
2 |
|
T5 |
20 |
|
T8 |
7 |
| others[1] |
781 |
1 |
|
T5 |
20 |
|
T7 |
1 |
|
T8 |
6 |
| others[2] |
799 |
1 |
|
T5 |
11 |
|
T7 |
1 |
|
T8 |
10 |
| others[3] |
1332 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T5 |
36 |
| false |
401 |
1 |
|
T5 |
14 |
|
T8 |
8 |
|
T47 |
3 |
| true |
542 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2316 |
1 |
|
T12 |
2 |
|
T5 |
9 |
|
T8 |
11 |
| others[1] |
2426 |
1 |
|
T5 |
9 |
|
T7 |
3 |
|
T8 |
10 |
| others[2] |
2411 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T8 |
12 |
| others[3] |
4003 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T8 |
17 |
| false |
1173 |
1 |
|
T20 |
1 |
|
T5 |
3 |
|
T21 |
18 |
| true |
1571 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9523 |
1 |
|
T12 |
2 |
|
T5 |
10 |
|
T21 |
215 |
| others[1] |
265 |
1 |
|
T5 |
10 |
|
T22 |
1 |
|
T41 |
1 |
| others[2] |
272 |
1 |
|
T5 |
3 |
|
T22 |
1 |
|
T190 |
1 |
| others[3] |
465 |
1 |
|
T5 |
13 |
|
T7 |
1 |
|
T40 |
1 |
| false |
155 |
1 |
|
T20 |
1 |
|
T5 |
12 |
|
T7 |
1 |
| true |
3220 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9733 |
1 |
|
T12 |
2 |
|
T5 |
11 |
|
T8 |
3 |
| others[1] |
521 |
1 |
|
T5 |
6 |
|
T8 |
11 |
|
T47 |
3 |
| others[2] |
472 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T5 |
10 |
| others[3] |
772 |
1 |
|
T4 |
1 |
|
T5 |
16 |
|
T7 |
2 |
| false |
236 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T8 |
1 |
| true |
2166 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T5 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9565 |
1 |
|
T12 |
2 |
|
T5 |
10 |
|
T21 |
215 |
| others[1] |
261 |
1 |
|
T5 |
10 |
|
T7 |
1 |
|
T32 |
1 |
| others[2] |
287 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T5 |
11 |
| others[3] |
437 |
1 |
|
T5 |
14 |
|
T7 |
1 |
|
T33 |
1 |
| false |
119 |
1 |
|
T5 |
3 |
|
T74 |
1 |
|
T144 |
1 |
| true |
3231 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9517 |
1 |
|
T12 |
2 |
|
T5 |
7 |
|
T7 |
1 |
| others[1] |
229 |
1 |
|
T5 |
10 |
|
T416 |
1 |
|
T234 |
1 |
| others[2] |
246 |
1 |
|
T5 |
10 |
|
T22 |
1 |
|
T76 |
1 |
| others[3] |
414 |
1 |
|
T5 |
8 |
|
T7 |
1 |
|
T33 |
1 |
| false |
121 |
1 |
|
T5 |
5 |
|
T190 |
1 |
|
T31 |
5 |
| true |
3373 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10123 |
1 |
|
T12 |
2 |
|
T20 |
1 |
|
T5 |
23 |
| others[1] |
795 |
1 |
|
T5 |
17 |
|
T8 |
13 |
|
T47 |
6 |
| others[2] |
779 |
1 |
|
T5 |
22 |
|
T7 |
2 |
|
T8 |
10 |
| others[3] |
1316 |
1 |
|
T4 |
1 |
|
T5 |
31 |
|
T8 |
16 |
| false |
378 |
1 |
|
T5 |
8 |
|
T8 |
5 |
|
T140 |
1 |
| true |
509 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T6 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |