Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	226115	1		T1	430		T4	292		T12	1
auto[FlashEraseBank]	253368	1		T1	460		T4	388		T6	18

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	263856	1		T1	890		T4	680		T12	1
auto[FlashOpProgram]	196319	1		T5	460		T7	4		T14	2
auto[FlashOpErase]	15308	1		T6	31		T5	52		T7	2
auto[FlashOpInvalid]	4000	1		T95	200		T121	200		T222	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	263856	1		T1	890		T4	680		T12	1
op[FlashOpProgram]	196319	1		T5	460		T7	4		T14	2
op[FlashOpErase]	15308	1		T6	31		T5	52		T7	2
read_erase_read	743	1		T6	14		T5	2		T7	2
read_prog_read	1219	1		T5	1		T7	1		T24	6

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	338456	1		T1	761		T4	646		T6	29
auto[FlashPartInfo]	137361	1		T1	81		T12	1		T6	38
auto[FlashPartInfo1]	891	1		T1	18		T22	1		T40	1
auto[FlashPartInfo2]	2775	1		T1	30		T4	34		T6	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	200466	1		T1	761		T4	646		T6	11
auto[FlashPartData]	auto[FlashOpProgram]	130440	1		T5	42		T7	4		T25	2
auto[FlashPartData]	auto[FlashOpErase]	3634	1		T6	18		T5	36		T7	2
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T95	194		T121	198		T222	192
auto[FlashPartInfo]	auto[FlashOpRead]	60977	1		T1	81		T12	1		T6	25
auto[FlashPartInfo]	auto[FlashOpProgram]	64688	1		T5	418		T14	1		T24	6
auto[FlashPartInfo]	auto[FlashOpErase]	11624	1		T6	13		T5	16		T21	319
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T95	6		T121	2		T222	8
auto[FlashPartInfo1]	auto[FlashOpRead]	720	1		T1	18		T22	1		T40	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T97	32		T125	32		T43	1
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T132	1		T418	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T132	2		T418	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1693	1		T1	30		T4	34		T6	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	1026	1		T14	1		T22	1		T40	2
auto[FlashPartInfo2]	auto[FlashOpErase]	48	1		T286	35		T63	1		T43	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T419	2		T420	2		T421	2