Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	3	29	90.62

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	3	29	90.62	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29568	1		T5	16		T21	652		T90	432
auto[1]	15	1		T289	4		T49	1		T35	3
auto[2]	171	1		T285	18		T51	11		T344	3
auto[3]	168	1		T25	1		T26	1		T34	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7500	1		T5	4		T21	163		T25	1
evic_idx[1]	7500	1		T5	4		T21	163		T90	108
evic_idx[2]	7471	1		T5	4		T21	163		T90	108
evic_idx[3]	7451	1		T5	4		T21	163		T90	108

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28889	1		T21	652		T90	432		T92	392
evic_op[2]	503	1		T25	1		T26	1		T34	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	3	29	90.62	3

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[2]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[3]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7183	1		T21	163		T90	108		T92	98
evic_idx[0]	evic_op[1]	auto[2]	25	1		T345	25		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	33	1		T219	1		T346	10		T347	16
evic_idx[0]	evic_op[2]	auto[0]	81	1		T31	1		T184	1		T285	2
evic_idx[0]	evic_op[2]	auto[1]	5	1		T35	1		T112	1		T348	1
evic_idx[0]	evic_op[2]	auto[2]	24	1		T285	4		T51	3		T349	9
evic_idx[0]	evic_op[2]	auto[3]	15	1		T25	1		T26	1		T34	1
evic_idx[1]	evic_op[1]	auto[0]	7179	1		T21	163		T90	108		T92	98
evic_idx[1]	evic_op[1]	auto[1]	3	1		T289	3		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	12	1		T345	12		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	42	1		T219	3		T346	15		T347	18
evic_idx[1]	evic_op[2]	auto[0]	85	1		T31	1		T184	1		T285	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T35	1		T293	1		T350	1
evic_idx[1]	evic_op[2]	auto[2]	31	1		T285	7		T51	4		T344	3
evic_idx[1]	evic_op[2]	auto[3]	13	1		T230	1		T120	1		T208	1
evic_idx[2]	evic_op[1]	auto[0]	7181	1		T21	163		T90	108		T92	98
evic_idx[2]	evic_op[1]	auto[2]	8	1		T345	8		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	18	1		T346	3		T347	10		T351	5
evic_idx[2]	evic_op[2]	auto[0]	83	1		T31	1		T184	1		T66	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T49	1		T35	1		T352	1
evic_idx[2]	evic_op[2]	auto[2]	28	1		T285	3		T51	2		T112	1
evic_idx[2]	evic_op[2]	auto[3]	18	1		T133	1		T208	1		T122	1
evic_idx[3]	evic_op[1]	auto[0]	7180	1		T21	163		T90	108		T92	98
evic_idx[3]	evic_op[1]	auto[1]	1	1		T289	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	7	1		T345	7		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	17	1		T346	3		T347	9		T351	5
evic_idx[3]	evic_op[2]	auto[0]	82	1		T31	1		T184	1		T124	1
evic_idx[3]	evic_op[2]	auto[2]	20	1		T285	4		T51	2		T349	8
evic_idx[3]	evic_op[2]	auto[3]	12	1		T133	1		T208	1		T353	1