Summary for Variable instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for instr_type_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| others | 
5901 | 
1 | 
 | 
T8 | 
124 | 
 | 
T47 | 
52 | 
 | 
T48 | 
105 | 
| instr_types[0] | 
7393 | 
1 | 
 | 
T8 | 
260 | 
 | 
T47 | 
212 | 
 | 
T48 | 
162 | 
| instr_types[1] | 
4615770 | 
1 | 
 | 
T1 | 
16177 | 
 | 
T4 | 
16300 | 
 | 
T6 | 
13 | 
Summary for Variable key_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for key_cp
Bins
| NAME | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4627144 | 
1 | 
 | 
T1 | 
16177 | 
 | 
T4 | 
16300 | 
 | 
T6 | 
13 | 
| auto[1] | 
1920 | 
1 | 
 | 
T8 | 
197 | 
 | 
T47 | 
122 | 
 | 
T48 | 
131 | 
Summary for Cross key_instr_cross
Samples crossed: key_cp instr_type_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for key_instr_cross
Bins
| key_cp | instr_type_cp | COUNT | AT LEAST |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
others | 
5545 | 
1 | 
 | 
T8 | 
61 | 
 | 
T47 | 
23 | 
 | 
T48 | 
105 | 
| auto[0] | 
instr_types[0] | 
6473 | 
1 | 
 | 
T8 | 
175 | 
 | 
T47 | 
161 | 
 | 
T48 | 
66 | 
| auto[0] | 
instr_types[1] | 
4615126 | 
1 | 
 | 
T1 | 
16177 | 
 | 
T4 | 
16300 | 
 | 
T6 | 
13 | 
| auto[1] | 
others | 
356 | 
1 | 
 | 
T8 | 
63 | 
 | 
T47 | 
29 | 
 | 
T52 | 
73 | 
| auto[1] | 
instr_types[0] | 
920 | 
1 | 
 | 
T8 | 
85 | 
 | 
T47 | 
51 | 
 | 
T48 | 
96 | 
| auto[1] | 
instr_types[1] | 
644 | 
1 | 
 | 
T8 | 
49 | 
 | 
T47 | 
42 | 
 | 
T48 | 
35 |