Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	34282	1		T33	8316		T338	9225		T339	2474
rd_lvl[2]	30024	1		T33	4260		T138	1689		T221	1125
rd_lvl[3]	18741	1		T138	1535		T221	1459		T340	1504
rd_lvl[4]	24791	1		T138	424		T221	187		T340	311
rd_lvl[5]	14993	1		T138	1271		T221	915		T340	1313
rd_lvl[6]	15498	1		T138	1635		T220	870		T243	1248
rd_lvl[7]	12135	1		T138	1		T220	504		T243	414
rd_lvl[8]	15127	1		T138	1		T220	106		T203	1378
rd_lvl[9]	8724	1		T1	165		T65	247		T144	508
rd_lvl[10]	7945	1		T1	704		T65	903		T144	367
rd_lvl[11]	5855	1		T138	1		T221	1		T341	301
rd_lvl[12]	4387	1		T1	21		T65	41		T138	60
rd_lvl[13]	6658	1		T32	579		T138	57		T342	591
rd_lvl[14]	6341	1		T32	520		T81	451		T342	373
rd_lvl[15]	4862	1		T4	451		T234	481		T81	242