Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	325880	1		T1	1781		T2	1		T3	1
all_pins[1]	325880	1		T1	1781		T2	1		T3	1
all_pins[2]	325880	1		T1	1781		T2	1		T3	1
all_pins[3]	325880	1		T1	1781		T2	1		T3	1
all_pins[4]	325880	1		T1	1781		T2	1		T3	1
all_pins[5]	325880	1		T1	1781		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1634835	1		T1	8906		T2	6		T3	6
values[0x1]	320445	1		T1	1780		T4	1818		T33	13661
transitions[0x0=>0x1]	291970	1		T1	1780		T4	1360		T33	12576
transitions[0x1=>0x0]	291950	1		T1	1780		T4	1360		T33	12576

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	325724	1		T1	1781		T2	1		T3	1
all_pins[0]	values[0x1]	156	1		T275	4		T276	2		T332	1
all_pins[0]	transitions[0x0=>0x1]	87	1		T275	3		T276	2		T332	1
all_pins[0]	transitions[0x1=>0x0]	79	1		T275	1		T277	6		T332	6
all_pins[1]	values[0x0]	325732	1		T1	1781		T2	1		T3	1
all_pins[1]	values[0x1]	148	1		T275	2		T277	6		T332	6
all_pins[1]	transitions[0x0=>0x1]	122	1		T275	1		T277	5		T332	4
all_pins[1]	transitions[0x1=>0x0]	2737	1		T4	229		T234	320		T354	313
all_pins[2]	values[0x0]	323117	1		T1	1781		T2	1		T3	1
all_pins[2]	values[0x1]	2763	1		T4	229		T234	320		T354	313
all_pins[2]	transitions[0x0=>0x1]	42	1		T276	3		T277	1		T332	2
all_pins[2]	transitions[0x1=>0x0]	211322	1		T1	890		T4	451		T33	12576
all_pins[3]	values[0x0]	111837	1		T1	891		T2	1		T3	1
all_pins[3]	values[0x1]	214043	1		T1	890		T4	680		T33	12576
all_pins[3]	transitions[0x0=>0x1]	188426	1		T1	890		T4	451		T33	11491
all_pins[3]	transitions[0x1=>0x0]	77662	1		T1	890		T4	680		T32	1173
all_pins[4]	values[0x0]	222601	1		T1	891		T2	1		T3	1
all_pins[4]	values[0x1]	103279	1		T1	890		T4	909		T33	1085
all_pins[4]	transitions[0x0=>0x1]	103268	1		T1	890		T4	909		T33	1085
all_pins[4]	transitions[0x1=>0x0]	45	1		T275	3		T332	2		T343	1
all_pins[5]	values[0x0]	325824	1		T1	1781		T2	1		T3	1
all_pins[5]	values[0x1]	56	1		T275	3		T332	2		T343	1
all_pins[5]	transitions[0x0=>0x1]	25	1		T275	1		T332	2		T355	1
all_pins[5]	transitions[0x1=>0x0]	105	1		T275	1		T276	1		T332	1