| T1084 |
/workspace/coverage/default/5.flash_ctrl_alert_test.2461535304 |
|
|
Mar 17 01:10:54 PM PDT 24 |
Mar 17 01:11:08 PM PDT 24 |
67517700 ps |
| T1085 |
/workspace/coverage/default/1.flash_ctrl_invalid_op.4185807754 |
|
|
Mar 17 01:10:35 PM PDT 24 |
Mar 17 01:11:45 PM PDT 24 |
8779457900 ps |
| T1086 |
/workspace/coverage/default/37.flash_ctrl_intr_rd.181698382 |
|
|
Mar 17 01:13:51 PM PDT 24 |
Mar 17 01:16:54 PM PDT 24 |
1940876200 ps |
| T1087 |
/workspace/coverage/default/31.flash_ctrl_disable.2437396472 |
|
|
Mar 17 01:13:34 PM PDT 24 |
Mar 17 01:13:56 PM PDT 24 |
16146200 ps |
| T1088 |
/workspace/coverage/default/30.flash_ctrl_smoke.3007689304 |
|
|
Mar 17 01:13:26 PM PDT 24 |
Mar 17 01:15:56 PM PDT 24 |
32452400 ps |
| T1089 |
/workspace/coverage/default/31.flash_ctrl_alert_test.3563373933 |
|
|
Mar 17 01:13:33 PM PDT 24 |
Mar 17 01:13:47 PM PDT 24 |
119463400 ps |
| T1090 |
/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.1808957595 |
|
|
Mar 17 01:11:05 PM PDT 24 |
Mar 17 01:11:37 PM PDT 24 |
28227700 ps |
| T38 |
/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.3085780649 |
|
|
Mar 17 01:10:18 PM PDT 24 |
Mar 17 01:10:32 PM PDT 24 |
14899400 ps |
| T1091 |
/workspace/coverage/default/30.flash_ctrl_connect.790820384 |
|
|
Mar 17 01:13:48 PM PDT 24 |
Mar 17 01:14:01 PM PDT 24 |
27725300 ps |
| T1092 |
/workspace/coverage/default/3.flash_ctrl_sw_op.1450494037 |
|
|
Mar 17 01:10:45 PM PDT 24 |
Mar 17 01:11:11 PM PDT 24 |
78280800 ps |
| T1093 |
/workspace/coverage/default/68.flash_ctrl_otp_reset.3582409275 |
|
|
Mar 17 01:14:32 PM PDT 24 |
Mar 17 01:16:25 PM PDT 24 |
516476300 ps |
| T1094 |
/workspace/coverage/default/37.flash_ctrl_alert_test.1515113428 |
|
|
Mar 17 01:13:56 PM PDT 24 |
Mar 17 01:14:10 PM PDT 24 |
23867000 ps |
| T1095 |
/workspace/coverage/default/8.flash_ctrl_alert_test.3598940299 |
|
|
Mar 17 01:11:29 PM PDT 24 |
Mar 17 01:11:45 PM PDT 24 |
84298400 ps |
| T1096 |
/workspace/coverage/default/25.flash_ctrl_sec_info_access.1467814075 |
|
|
Mar 17 01:13:03 PM PDT 24 |
Mar 17 01:13:56 PM PDT 24 |
366337600 ps |
| T1097 |
/workspace/coverage/default/1.flash_ctrl_alert_test.3320991230 |
|
|
Mar 17 01:10:37 PM PDT 24 |
Mar 17 01:10:51 PM PDT 24 |
46350800 ps |
| T1098 |
/workspace/coverage/default/0.flash_ctrl_config_regwen.1619788122 |
|
|
Mar 17 01:10:26 PM PDT 24 |
Mar 17 01:10:40 PM PDT 24 |
37198700 ps |
| T1099 |
/workspace/coverage/default/4.flash_ctrl_intr_rd.2271067593 |
|
|
Mar 17 01:10:47 PM PDT 24 |
Mar 17 01:13:40 PM PDT 24 |
3177508200 ps |
| T1100 |
/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.108398023 |
|
|
Mar 17 01:13:10 PM PDT 24 |
Mar 17 01:15:22 PM PDT 24 |
30174743000 ps |
| T1101 |
/workspace/coverage/default/79.flash_ctrl_connect.1287754460 |
|
|
Mar 17 01:14:39 PM PDT 24 |
Mar 17 01:14:57 PM PDT 24 |
16219700 ps |
| T1102 |
/workspace/coverage/default/6.flash_ctrl_invalid_op.2667976434 |
|
|
Mar 17 01:11:01 PM PDT 24 |
Mar 17 01:12:06 PM PDT 24 |
9004838800 ps |
| T1103 |
/workspace/coverage/default/30.flash_ctrl_disable.3659488973 |
|
|
Mar 17 01:13:26 PM PDT 24 |
Mar 17 01:13:48 PM PDT 24 |
17430900 ps |
| T1104 |
/workspace/coverage/default/8.flash_ctrl_ro.3393486183 |
|
|
Mar 17 01:11:27 PM PDT 24 |
Mar 17 01:13:14 PM PDT 24 |
1972495300 ps |
| T350 |
/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2335507527 |
|
|
Mar 17 01:13:51 PM PDT 24 |
Mar 17 01:14:20 PM PDT 24 |
32298000 ps |
| T1105 |
/workspace/coverage/default/25.flash_ctrl_rw_evict.4238326786 |
|
|
Mar 17 01:13:05 PM PDT 24 |
Mar 17 01:13:37 PM PDT 24 |
137767200 ps |
| T1106 |
/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.1028111545 |
|
|
Mar 17 01:13:59 PM PDT 24 |
Mar 17 01:14:27 PM PDT 24 |
46886000 ps |
| T1107 |
/workspace/coverage/default/46.flash_ctrl_sec_info_access.4190703981 |
|
|
Mar 17 01:14:19 PM PDT 24 |
Mar 17 01:15:35 PM PDT 24 |
12849445000 ps |
| T1108 |
/workspace/coverage/default/22.flash_ctrl_otp_reset.703528813 |
|
|
Mar 17 01:12:52 PM PDT 24 |
Mar 17 01:15:08 PM PDT 24 |
65294300 ps |
| T1109 |
/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.727456233 |
|
|
Mar 17 01:10:32 PM PDT 24 |
Mar 17 01:17:13 PM PDT 24 |
91349017900 ps |
| T1110 |
/workspace/coverage/default/20.flash_ctrl_sec_info_access.683776330 |
|
|
Mar 17 01:12:46 PM PDT 24 |
Mar 17 01:13:58 PM PDT 24 |
1908422100 ps |
| T1111 |
/workspace/coverage/default/2.flash_ctrl_smoke.1089817941 |
|
|
Mar 17 01:10:30 PM PDT 24 |
Mar 17 01:12:58 PM PDT 24 |
29134600 ps |
| T1112 |
/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3412478085 |
|
|
Mar 17 01:14:10 PM PDT 24 |
Mar 17 01:16:27 PM PDT 24 |
5570953800 ps |
| T45 |
/workspace/coverage/default/1.flash_ctrl_access_after_disable.982615171 |
|
|
Mar 17 01:10:25 PM PDT 24 |
Mar 17 01:10:39 PM PDT 24 |
21881500 ps |
| T1113 |
/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.3795601464 |
|
|
Mar 17 01:10:51 PM PDT 24 |
Mar 17 01:11:05 PM PDT 24 |
15362300 ps |
| T1114 |
/workspace/coverage/default/10.flash_ctrl_ro.1842231200 |
|
|
Mar 17 01:11:38 PM PDT 24 |
Mar 17 01:13:20 PM PDT 24 |
527216400 ps |
| T1115 |
/workspace/coverage/default/11.flash_ctrl_otp_reset.2125849990 |
|
|
Mar 17 01:11:43 PM PDT 24 |
Mar 17 01:13:35 PM PDT 24 |
40961800 ps |
| T1116 |
/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1385056599 |
|
|
Mar 17 01:10:36 PM PDT 24 |
Mar 17 01:12:46 PM PDT 24 |
1420329300 ps |
| T1117 |
/workspace/coverage/default/79.flash_ctrl_otp_reset.29934178 |
|
|
Mar 17 01:14:40 PM PDT 24 |
Mar 17 01:16:55 PM PDT 24 |
70868700 ps |
| T411 |
/workspace/coverage/default/19.flash_ctrl_sec_info_access.2411981253 |
|
|
Mar 17 01:12:45 PM PDT 24 |
Mar 17 01:13:59 PM PDT 24 |
3734959800 ps |
| T1118 |
/workspace/coverage/default/11.flash_ctrl_ro.799332805 |
|
|
Mar 17 01:11:43 PM PDT 24 |
Mar 17 01:13:24 PM PDT 24 |
493358500 ps |
| T1119 |
/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.383745690 |
|
|
Mar 17 01:13:49 PM PDT 24 |
Mar 17 01:17:30 PM PDT 24 |
43363231500 ps |
| T1120 |
/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1604955674 |
|
|
Mar 17 01:11:33 PM PDT 24 |
Mar 17 01:14:04 PM PDT 24 |
3296010200 ps |
| T1121 |
/workspace/coverage/default/18.flash_ctrl_ro.2613539766 |
|
|
Mar 17 01:12:35 PM PDT 24 |
Mar 17 01:14:24 PM PDT 24 |
945374200 ps |
| T105 |
/workspace/coverage/default/17.flash_ctrl_mp_regions.81645331 |
|
|
Mar 17 01:12:27 PM PDT 24 |
Mar 17 01:17:18 PM PDT 24 |
10045254900 ps |
| T1122 |
/workspace/coverage/default/44.flash_ctrl_sec_info_access.504225668 |
|
|
Mar 17 01:14:13 PM PDT 24 |
Mar 17 01:15:15 PM PDT 24 |
564852300 ps |
| T1123 |
/workspace/coverage/default/6.flash_ctrl_alert_test.561078846 |
|
|
Mar 17 01:11:06 PM PDT 24 |
Mar 17 01:11:20 PM PDT 24 |
32542200 ps |
| T304 |
/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.994431160 |
|
|
Mar 17 01:12:08 PM PDT 24 |
Mar 17 01:12:56 PM PDT 24 |
10035067700 ps |
| T106 |
/workspace/coverage/default/14.flash_ctrl_mp_regions.1431839503 |
|
|
Mar 17 01:11:57 PM PDT 24 |
Mar 17 01:16:03 PM PDT 24 |
58287114000 ps |
| T1124 |
/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3885470634 |
|
|
Mar 17 01:13:17 PM PDT 24 |
Mar 17 01:14:20 PM PDT 24 |
1601507600 ps |
| T1125 |
/workspace/coverage/default/10.flash_ctrl_rand_ops.461777245 |
|
|
Mar 17 01:11:36 PM PDT 24 |
Mar 17 01:12:57 PM PDT 24 |
20346800 ps |
| T1126 |
/workspace/coverage/default/0.flash_ctrl_phy_arb.2655357042 |
|
|
Mar 17 01:10:15 PM PDT 24 |
Mar 17 01:14:14 PM PDT 24 |
192644400 ps |
| T1127 |
/workspace/coverage/default/10.flash_ctrl_disable.1806557851 |
|
|
Mar 17 01:11:35 PM PDT 24 |
Mar 17 01:11:58 PM PDT 24 |
63651000 ps |
| T1128 |
/workspace/coverage/default/9.flash_ctrl_ro.3136404108 |
|
|
Mar 17 01:11:28 PM PDT 24 |
Mar 17 01:13:11 PM PDT 24 |
497538400 ps |
| T1129 |
/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.2546785404 |
|
|
Mar 17 01:11:11 PM PDT 24 |
Mar 17 01:23:32 PM PDT 24 |
80137208900 ps |
| T1130 |
/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1558402235 |
|
|
Mar 17 01:10:16 PM PDT 24 |
Mar 17 01:23:32 PM PDT 24 |
120151433800 ps |
| T1131 |
/workspace/coverage/default/9.flash_ctrl_alert_test.3825821764 |
|
|
Mar 17 01:11:37 PM PDT 24 |
Mar 17 01:11:51 PM PDT 24 |
237355100 ps |
| T1132 |
/workspace/coverage/default/40.flash_ctrl_smoke.3374074706 |
|
|
Mar 17 01:14:03 PM PDT 24 |
Mar 17 01:17:17 PM PDT 24 |
150662500 ps |
| T1133 |
/workspace/coverage/default/1.flash_ctrl_intr_rd.1558026466 |
|
|
Mar 17 01:10:26 PM PDT 24 |
Mar 17 01:13:57 PM PDT 24 |
1086405300 ps |
| T1134 |
/workspace/coverage/default/0.flash_ctrl_fetch_code.567963385 |
|
|
Mar 17 01:10:17 PM PDT 24 |
Mar 17 01:10:43 PM PDT 24 |
384795400 ps |
| T1135 |
/workspace/coverage/default/15.flash_ctrl_ro.2138762332 |
|
|
Mar 17 01:12:12 PM PDT 24 |
Mar 17 01:13:35 PM PDT 24 |
685358600 ps |
| T1136 |
/workspace/coverage/default/42.flash_ctrl_otp_reset.3821700095 |
|
|
Mar 17 01:14:12 PM PDT 24 |
Mar 17 01:16:07 PM PDT 24 |
43508000 ps |
| T1137 |
/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.4232306886 |
|
|
Mar 17 01:12:49 PM PDT 24 |
Mar 17 01:13:21 PM PDT 24 |
67011600 ps |
| T275 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1410454484 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:17 PM PDT 24 |
21586900 ps |
| T276 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2148225443 |
|
|
Mar 17 01:02:42 PM PDT 24 |
Mar 17 01:02:56 PM PDT 24 |
51538300 ps |
| T56 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.31887618 |
|
|
Mar 17 01:02:34 PM PDT 24 |
Mar 17 01:02:48 PM PDT 24 |
151403900 ps |
| T57 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2706851436 |
|
|
Mar 17 01:02:01 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
2919467300 ps |
| T277 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3123073820 |
|
|
Mar 17 01:02:41 PM PDT 24 |
Mar 17 01:02:55 PM PDT 24 |
18355700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3144830080 |
|
|
Mar 17 01:02:09 PM PDT 24 |
Mar 17 01:02:25 PM PDT 24 |
106618400 ps |
| T332 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2237682391 |
|
|
Mar 17 01:01:57 PM PDT 24 |
Mar 17 01:02:11 PM PDT 24 |
14711800 ps |
| T1139 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1747715835 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:38 PM PDT 24 |
23450600 ps |
| T195 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1156836610 |
|
|
Mar 17 01:02:05 PM PDT 24 |
Mar 17 01:02:21 PM PDT 24 |
55992900 ps |
| T58 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.159975180 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:37 PM PDT 24 |
87676800 ps |
| T237 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3838671779 |
|
|
Mar 17 01:01:59 PM PDT 24 |
Mar 17 01:02:25 PM PDT 24 |
58258800 ps |
| T333 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1090522969 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
30484900 ps |
| T263 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1408371639 |
|
|
Mar 17 01:02:39 PM PDT 24 |
Mar 17 01:03:00 PM PDT 24 |
267644400 ps |
| T1140 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4285650926 |
|
|
Mar 17 01:02:25 PM PDT 24 |
Mar 17 01:02:41 PM PDT 24 |
12494400 ps |
| T343 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2177152456 |
|
|
Mar 17 01:02:43 PM PDT 24 |
Mar 17 01:02:57 PM PDT 24 |
149407700 ps |
| T198 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1140206699 |
|
|
Mar 17 01:02:32 PM PDT 24 |
Mar 17 01:02:52 PM PDT 24 |
54537000 ps |
| T1141 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1412650063 |
|
|
Mar 17 01:02:16 PM PDT 24 |
Mar 17 01:02:32 PM PDT 24 |
21437000 ps |
| T235 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3364497038 |
|
|
Mar 17 01:02:17 PM PDT 24 |
Mar 17 01:02:34 PM PDT 24 |
126242800 ps |
| T264 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2638024473 |
|
|
Mar 17 01:02:34 PM PDT 24 |
Mar 17 01:02:55 PM PDT 24 |
163463600 ps |
| T1142 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1342213209 |
|
|
Mar 17 01:02:14 PM PDT 24 |
Mar 17 01:02:30 PM PDT 24 |
12896000 ps |
| T236 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.944972225 |
|
|
Mar 17 01:02:02 PM PDT 24 |
Mar 17 01:02:20 PM PDT 24 |
154884400 ps |
| T265 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2303879328 |
|
|
Mar 17 01:02:14 PM PDT 24 |
Mar 17 01:02:35 PM PDT 24 |
639905400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4226000956 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:34 PM PDT 24 |
157197200 ps |
| T335 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3907534156 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
15747200 ps |
| T271 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3195463650 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:44 PM PDT 24 |
1489839300 ps |
| T272 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.449514618 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:03:29 PM PDT 24 |
4863768900 ps |
| T336 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2835923853 |
|
|
Mar 17 01:02:35 PM PDT 24 |
Mar 17 01:02:50 PM PDT 24 |
53920800 ps |
| T334 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.810537409 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:36 PM PDT 24 |
35310700 ps |
| T196 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.751358007 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:08:49 PM PDT 24 |
1398506100 ps |
| T266 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3317843670 |
|
|
Mar 17 01:02:31 PM PDT 24 |
Mar 17 01:02:48 PM PDT 24 |
35759700 ps |
| T1144 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2871123715 |
|
|
Mar 17 01:02:17 PM PDT 24 |
Mar 17 01:02:34 PM PDT 24 |
336569600 ps |
| T370 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2395213213 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
34590200 ps |
| T1145 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2830343740 |
|
|
Mar 17 01:02:20 PM PDT 24 |
Mar 17 01:02:40 PM PDT 24 |
317562800 ps |
| T197 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.471407843 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
83585400 ps |
| T313 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1678709191 |
|
|
Mar 17 01:02:05 PM PDT 24 |
Mar 17 01:02:44 PM PDT 24 |
613440400 ps |
| T1146 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2751409262 |
|
|
Mar 17 01:02:40 PM PDT 24 |
Mar 17 01:02:54 PM PDT 24 |
164060400 ps |
| T355 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3322327926 |
|
|
Mar 17 01:01:56 PM PDT 24 |
Mar 17 01:02:10 PM PDT 24 |
151735900 ps |
| T308 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.155806845 |
|
|
Mar 17 01:01:57 PM PDT 24 |
Mar 17 01:02:11 PM PDT 24 |
159179700 ps |
| T337 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1707051393 |
|
|
Mar 17 01:02:10 PM PDT 24 |
Mar 17 01:02:23 PM PDT 24 |
31199300 ps |
| T1147 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3839403341 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:32 PM PDT 24 |
11929900 ps |
| T1148 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.232885991 |
|
|
Mar 17 01:02:16 PM PDT 24 |
Mar 17 01:02:32 PM PDT 24 |
32360000 ps |
| T371 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.599779516 |
|
|
Mar 17 01:02:36 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
111084700 ps |
| T309 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2141591230 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:35 PM PDT 24 |
218896800 ps |
| T246 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1183199738 |
|
|
Mar 17 01:02:11 PM PDT 24 |
Mar 17 01:02:30 PM PDT 24 |
155995800 ps |
| T310 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1022505201 |
|
|
Mar 17 01:02:30 PM PDT 24 |
Mar 17 01:02:49 PM PDT 24 |
496683800 ps |
| T250 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.676130692 |
|
|
Mar 17 01:02:02 PM PDT 24 |
Mar 17 01:02:20 PM PDT 24 |
71569900 ps |
| T247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2660000903 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:23 PM PDT 24 |
108606200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.628892642 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:41 PM PDT 24 |
339627200 ps |
| T1150 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2172016511 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:32 PM PDT 24 |
16051700 ps |
| T1151 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3932562899 |
|
|
Mar 17 01:02:49 PM PDT 24 |
Mar 17 01:03:04 PM PDT 24 |
60679200 ps |
| T1152 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3906994796 |
|
|
Mar 17 01:02:41 PM PDT 24 |
Mar 17 01:02:55 PM PDT 24 |
17783200 ps |
| T1153 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2195289891 |
|
|
Mar 17 01:02:43 PM PDT 24 |
Mar 17 01:02:57 PM PDT 24 |
27399500 ps |
| T1154 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2899208475 |
|
|
Mar 17 01:01:55 PM PDT 24 |
Mar 17 01:02:11 PM PDT 24 |
38219600 ps |
| T1155 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3528126157 |
|
|
Mar 17 01:02:43 PM PDT 24 |
Mar 17 01:02:57 PM PDT 24 |
17264500 ps |
| T1156 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.357833005 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:18 PM PDT 24 |
26003900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.55599162 |
|
|
Mar 17 01:02:17 PM PDT 24 |
Mar 17 01:02:31 PM PDT 24 |
24414300 ps |
| T251 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.537221293 |
|
|
Mar 17 01:02:24 PM PDT 24 |
Mar 17 01:10:09 PM PDT 24 |
548867700 ps |
| T311 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1524271496 |
|
|
Mar 17 01:02:17 PM PDT 24 |
Mar 17 01:02:31 PM PDT 24 |
43542800 ps |
| T312 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2056718000 |
|
|
Mar 17 01:02:02 PM PDT 24 |
Mar 17 01:02:29 PM PDT 24 |
149363500 ps |
| T1158 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.423058996 |
|
|
Mar 17 01:02:30 PM PDT 24 |
Mar 17 01:02:44 PM PDT 24 |
47206000 ps |
| T1159 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3089303613 |
|
|
Mar 17 01:02:30 PM PDT 24 |
Mar 17 01:02:48 PM PDT 24 |
150484200 ps |
| T1160 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2115425235 |
|
|
Mar 17 01:02:09 PM PDT 24 |
Mar 17 01:02:25 PM PDT 24 |
24178100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3559342563 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:21 PM PDT 24 |
289415400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1463956213 |
|
|
Mar 17 01:02:36 PM PDT 24 |
Mar 17 01:02:50 PM PDT 24 |
18663200 ps |
| T372 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2205981610 |
|
|
Mar 17 01:02:06 PM PDT 24 |
Mar 17 01:03:09 PM PDT 24 |
2912789500 ps |
| T248 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3169695320 |
|
|
Mar 17 01:02:14 PM PDT 24 |
Mar 17 01:02:30 PM PDT 24 |
37348700 ps |
| T249 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2874340214 |
|
|
Mar 17 01:02:27 PM PDT 24 |
Mar 17 01:17:36 PM PDT 24 |
836867300 ps |
| T1163 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1647655492 |
|
|
Mar 17 01:02:15 PM PDT 24 |
Mar 17 01:02:31 PM PDT 24 |
70887200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1079354304 |
|
|
Mar 17 01:02:30 PM PDT 24 |
Mar 17 01:02:44 PM PDT 24 |
22730300 ps |
| T1165 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2102318726 |
|
|
Mar 17 01:02:43 PM PDT 24 |
Mar 17 01:02:57 PM PDT 24 |
15899400 ps |
| T273 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.636370156 |
|
|
Mar 17 01:02:38 PM PDT 24 |
Mar 17 01:02:57 PM PDT 24 |
52329900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3457112923 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
53079000 ps |
| T1167 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.708317862 |
|
|
Mar 17 01:02:06 PM PDT 24 |
Mar 17 01:02:44 PM PDT 24 |
640686700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.162282458 |
|
|
Mar 17 01:02:12 PM PDT 24 |
Mar 17 01:02:30 PM PDT 24 |
73374000 ps |
| T1169 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.127253435 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:37 PM PDT 24 |
45702900 ps |
| T252 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4044860697 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:17 PM PDT 24 |
168094800 ps |
| T274 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3708229998 |
|
|
Mar 17 01:02:30 PM PDT 24 |
Mar 17 01:02:48 PM PDT 24 |
456950100 ps |
| T253 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2659912956 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:17 PM PDT 24 |
34689900 ps |
| T314 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.509776629 |
|
|
Mar 17 01:02:35 PM PDT 24 |
Mar 17 01:02:56 PM PDT 24 |
383704600 ps |
| T357 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.818493869 |
|
|
Mar 17 01:02:25 PM PDT 24 |
Mar 17 01:10:03 PM PDT 24 |
1326535500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.431125630 |
|
|
Mar 17 01:02:16 PM PDT 24 |
Mar 17 01:02:32 PM PDT 24 |
43471400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2541846941 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:38 PM PDT 24 |
61064500 ps |
| T1172 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2785998793 |
|
|
Mar 17 01:02:14 PM PDT 24 |
Mar 17 01:02:48 PM PDT 24 |
222212100 ps |
| T278 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3627561909 |
|
|
Mar 17 01:01:57 PM PDT 24 |
Mar 17 01:09:42 PM PDT 24 |
373102100 ps |
| T1173 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1551171974 |
|
|
Mar 17 01:02:31 PM PDT 24 |
Mar 17 01:02:47 PM PDT 24 |
63275200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.885342519 |
|
|
Mar 17 01:02:36 PM PDT 24 |
Mar 17 01:02:50 PM PDT 24 |
24248500 ps |
| T1175 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3791390207 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
58757100 ps |
| T358 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2795407645 |
|
|
Mar 17 01:02:30 PM PDT 24 |
Mar 17 01:17:34 PM PDT 24 |
665277300 ps |
| T1176 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2052011010 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:53 PM PDT 24 |
11311400 ps |
| T1177 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.322869926 |
|
|
Mar 17 01:02:24 PM PDT 24 |
Mar 17 01:02:41 PM PDT 24 |
43351200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2301061082 |
|
|
Mar 17 01:02:23 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
13107100 ps |
| T1179 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.641607875 |
|
|
Mar 17 01:02:40 PM PDT 24 |
Mar 17 01:02:54 PM PDT 24 |
16654500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4127251150 |
|
|
Mar 17 01:02:24 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
197058200 ps |
| T1181 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2385452083 |
|
|
Mar 17 01:02:19 PM PDT 24 |
Mar 17 01:02:34 PM PDT 24 |
390896600 ps |
| T1182 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4101350695 |
|
|
Mar 17 01:02:09 PM PDT 24 |
Mar 17 01:02:25 PM PDT 24 |
47120900 ps |
| T1183 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2785467100 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:23 PM PDT 24 |
178598200 ps |
| T1184 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2461649592 |
|
|
Mar 17 01:02:30 PM PDT 24 |
Mar 17 01:02:46 PM PDT 24 |
11449800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4139008897 |
|
|
Mar 17 01:02:16 PM PDT 24 |
Mar 17 01:02:33 PM PDT 24 |
25796400 ps |
| T1186 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.269710127 |
|
|
Mar 17 01:02:10 PM PDT 24 |
Mar 17 01:02:25 PM PDT 24 |
621432700 ps |
| T1187 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1243579545 |
|
|
Mar 17 01:02:01 PM PDT 24 |
Mar 17 01:02:46 PM PDT 24 |
7212341500 ps |
| T254 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2675828032 |
|
|
Mar 17 01:01:56 PM PDT 24 |
Mar 17 01:02:10 PM PDT 24 |
42529500 ps |
| T1188 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2036247239 |
|
|
Mar 17 01:02:24 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
17371500 ps |
| T279 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2306502614 |
|
|
Mar 17 01:02:05 PM PDT 24 |
Mar 17 01:09:47 PM PDT 24 |
1799458800 ps |
| T1189 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2341131710 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
16168700 ps |
| T1190 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2740974953 |
|
|
Mar 17 01:02:42 PM PDT 24 |
Mar 17 01:02:56 PM PDT 24 |
41106500 ps |
| T1191 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.708577896 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:18 PM PDT 24 |
22449200 ps |
| T1192 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.808746858 |
|
|
Mar 17 01:02:01 PM PDT 24 |
Mar 17 01:03:04 PM PDT 24 |
752257400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3453757591 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
19086400 ps |
| T1194 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1818046387 |
|
|
Mar 17 01:02:23 PM PDT 24 |
Mar 17 01:02:37 PM PDT 24 |
38872600 ps |
| T1195 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1407782845 |
|
|
Mar 17 01:02:02 PM PDT 24 |
Mar 17 01:02:20 PM PDT 24 |
30067000 ps |
| T1196 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.237163453 |
|
|
Mar 17 01:02:35 PM PDT 24 |
Mar 17 01:02:49 PM PDT 24 |
49271100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.487490693 |
|
|
Mar 17 01:02:08 PM PDT 24 |
Mar 17 01:02:44 PM PDT 24 |
632624100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3601307276 |
|
|
Mar 17 01:02:25 PM PDT 24 |
Mar 17 01:02:42 PM PDT 24 |
69731500 ps |
| T1199 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.4167444530 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:35 PM PDT 24 |
70319300 ps |
| T281 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.414191753 |
|
|
Mar 17 01:02:24 PM PDT 24 |
Mar 17 01:02:43 PM PDT 24 |
54752900 ps |
| T369 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.675928033 |
|
|
Mar 17 01:02:23 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
1416817900 ps |
| T1200 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1811120824 |
|
|
Mar 17 01:02:36 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
45687700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2678123480 |
|
|
Mar 17 01:02:23 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
20113700 ps |
| T1202 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1878102895 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:19 PM PDT 24 |
14536900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1429744821 |
|
|
Mar 17 01:02:43 PM PDT 24 |
Mar 17 01:02:58 PM PDT 24 |
60652600 ps |
| T1204 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3472696091 |
|
|
Mar 17 01:02:16 PM PDT 24 |
Mar 17 01:02:31 PM PDT 24 |
17815000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.873439175 |
|
|
Mar 17 01:02:27 PM PDT 24 |
Mar 17 01:02:46 PM PDT 24 |
929608500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2648074909 |
|
|
Mar 17 01:01:55 PM PDT 24 |
Mar 17 01:02:09 PM PDT 24 |
51960000 ps |
| T315 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3803829421 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:03:14 PM PDT 24 |
1761353900 ps |
| T1207 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1109884910 |
|
|
Mar 17 01:02:06 PM PDT 24 |
Mar 17 01:02:19 PM PDT 24 |
78972600 ps |
| T1208 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2077477012 |
|
|
Mar 17 01:02:40 PM PDT 24 |
Mar 17 01:02:54 PM PDT 24 |
94044200 ps |
| T1209 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3019170408 |
|
|
Mar 17 01:02:31 PM PDT 24 |
Mar 17 01:02:47 PM PDT 24 |
26601900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.959796974 |
|
|
Mar 17 01:02:31 PM PDT 24 |
Mar 17 01:02:47 PM PDT 24 |
12796900 ps |
| T364 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1402517173 |
|
|
Mar 17 01:02:29 PM PDT 24 |
Mar 17 01:10:09 PM PDT 24 |
864730100 ps |
| T1211 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.266248489 |
|
|
Mar 17 01:02:16 PM PDT 24 |
Mar 17 01:02:34 PM PDT 24 |
207322300 ps |
| T1212 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3025591210 |
|
|
Mar 17 01:02:16 PM PDT 24 |
Mar 17 01:02:34 PM PDT 24 |
270623300 ps |
| T1213 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4139677361 |
|
|
Mar 17 01:02:02 PM PDT 24 |
Mar 17 01:02:24 PM PDT 24 |
1471135500 ps |
| T283 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1986293985 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:10:02 PM PDT 24 |
1681763800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.254849167 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:41 PM PDT 24 |
86935900 ps |
| T365 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3662935826 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:09:45 PM PDT 24 |
570929700 ps |
| T1215 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3031910115 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:35 PM PDT 24 |
27571400 ps |
| T1216 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2425258936 |
|
|
Mar 17 01:02:20 PM PDT 24 |
Mar 17 01:02:34 PM PDT 24 |
58297800 ps |
| T1217 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2418573327 |
|
|
Mar 17 01:02:09 PM PDT 24 |
Mar 17 01:02:26 PM PDT 24 |
130888000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1584711374 |
|
|
Mar 17 01:02:36 PM PDT 24 |
Mar 17 01:02:56 PM PDT 24 |
43683900 ps |
| T282 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2741603407 |
|
|
Mar 17 01:02:23 PM PDT 24 |
Mar 17 01:02:43 PM PDT 24 |
93273900 ps |
| T255 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.4253851745 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:18 PM PDT 24 |
18462600 ps |
| T1219 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3426186091 |
|
|
Mar 17 01:02:25 PM PDT 24 |
Mar 17 01:02:38 PM PDT 24 |
37129300 ps |
| T359 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3998717106 |
|
|
Mar 17 01:02:32 PM PDT 24 |
Mar 17 01:10:14 PM PDT 24 |
5626770900 ps |
| T316 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3950394399 |
|
|
Mar 17 01:02:14 PM PDT 24 |
Mar 17 01:03:00 PM PDT 24 |
93853700 ps |
| T1220 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4175129421 |
|
|
Mar 17 01:02:35 PM PDT 24 |
Mar 17 01:02:50 PM PDT 24 |
152103700 ps |
| T1221 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.908526810 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:35 PM PDT 24 |
148136100 ps |
| T1222 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1136070318 |
|
|
Mar 17 01:01:56 PM PDT 24 |
Mar 17 01:02:12 PM PDT 24 |
62978000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.525840585 |
|
|
Mar 17 01:02:05 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
170119000 ps |
| T317 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1494975120 |
|
|
Mar 17 01:02:32 PM PDT 24 |
Mar 17 01:02:52 PM PDT 24 |
158667600 ps |
| T1224 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1926507793 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:17 PM PDT 24 |
95704000 ps |
| T1225 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.663172402 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:34 PM PDT 24 |
15450500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3591289619 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:19 PM PDT 24 |
13145500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.922903974 |
|
|
Mar 17 01:01:58 PM PDT 24 |
Mar 17 01:03:02 PM PDT 24 |
2535318800 ps |
| T1228 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.319303409 |
|
|
Mar 17 01:02:09 PM PDT 24 |
Mar 17 01:02:25 PM PDT 24 |
35947600 ps |
| T318 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.624815335 |
|
|
Mar 17 01:02:25 PM PDT 24 |
Mar 17 01:02:42 PM PDT 24 |
60082900 ps |
| T1229 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1516133918 |
|
|
Mar 17 01:02:25 PM PDT 24 |
Mar 17 01:02:41 PM PDT 24 |
23163100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2965881419 |
|
|
Mar 17 01:02:29 PM PDT 24 |
Mar 17 01:02:46 PM PDT 24 |
33275700 ps |
| T368 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3033715093 |
|
|
Mar 17 01:02:36 PM PDT 24 |
Mar 17 01:09:04 PM PDT 24 |
183875100 ps |
| T1231 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1387588116 |
|
|
Mar 17 01:02:09 PM PDT 24 |
Mar 17 01:02:28 PM PDT 24 |
191315300 ps |
| T1232 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3895820668 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:20 PM PDT 24 |
15804600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1287696150 |
|
|
Mar 17 01:02:00 PM PDT 24 |
Mar 17 01:02:14 PM PDT 24 |
57243800 ps |
| T1234 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.109162214 |
|
|
Mar 17 01:02:41 PM PDT 24 |
Mar 17 01:02:55 PM PDT 24 |
144309900 ps |
| T356 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2528416794 |
|
|
Mar 17 01:02:22 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
243218500 ps |
| T1235 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.820307493 |
|
|
Mar 17 01:02:33 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
105082300 ps |
| T1236 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1808329641 |
|
|
Mar 17 01:02:36 PM PDT 24 |
Mar 17 01:02:50 PM PDT 24 |
38234100 ps |
| T1237 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2973632998 |
|
|
Mar 17 01:02:19 PM PDT 24 |
Mar 17 01:02:36 PM PDT 24 |
75762200 ps |
| T1238 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.4191323012 |
|
|
Mar 17 01:02:24 PM PDT 24 |
Mar 17 01:02:38 PM PDT 24 |
18818500 ps |
| T280 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.552458450 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:38 PM PDT 24 |
213014600 ps |
| T1239 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3814013081 |
|
|
Mar 17 01:02:09 PM PDT 24 |
Mar 17 01:02:29 PM PDT 24 |
109470200 ps |
| T284 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2780408712 |
|
|
Mar 17 01:02:12 PM PDT 24 |
Mar 17 01:08:39 PM PDT 24 |
418880300 ps |
| T1240 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1828034213 |
|
|
Mar 17 01:02:17 PM PDT 24 |
Mar 17 01:02:38 PM PDT 24 |
108241900 ps |
| T1241 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3290317868 |
|
|
Mar 17 01:02:05 PM PDT 24 |
Mar 17 01:02:23 PM PDT 24 |
156698800 ps |
| T1242 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3099345282 |
|
|
Mar 17 01:02:30 PM PDT 24 |
Mar 17 01:02:44 PM PDT 24 |
12288300 ps |
| T1243 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2261759192 |
|
|
Mar 17 01:02:14 PM PDT 24 |
Mar 17 01:02:27 PM PDT 24 |
14390600 ps |
| T1244 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4223372550 |
|
|
Mar 17 01:02:24 PM PDT 24 |
Mar 17 01:02:39 PM PDT 24 |
470500700 ps |
| T361 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1872588366 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:17:38 PM PDT 24 |
819596900 ps |
| T1245 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4252886576 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
33235300 ps |
| T1246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1041302577 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:20 PM PDT 24 |
14013200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1649731755 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:02:35 PM PDT 24 |
216486300 ps |
| T1248 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3533154799 |
|
|
Mar 17 01:02:14 PM PDT 24 |
Mar 17 01:02:28 PM PDT 24 |
76495000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2937433430 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:51 PM PDT 24 |
39438200 ps |
| T1250 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1969966955 |
|
|
Mar 17 01:02:37 PM PDT 24 |
Mar 17 01:02:50 PM PDT 24 |
22390100 ps |
| T1251 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2759117337 |
|
|
Mar 17 01:02:31 PM PDT 24 |
Mar 17 01:02:45 PM PDT 24 |
18574600 ps |
| T1252 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1714724385 |
|
|
Mar 17 01:02:28 PM PDT 24 |
Mar 17 01:02:49 PM PDT 24 |
117517400 ps |
| T366 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2810866386 |
|
|
Mar 17 01:02:18 PM PDT 24 |
Mar 17 01:17:21 PM PDT 24 |
1333682800 ps |
| T1253 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1271899126 |
|
|
Mar 17 01:01:59 PM PDT 24 |
Mar 17 01:02:13 PM PDT 24 |
12548600 ps |
| T1254 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1507350662 |
|
|
Mar 17 01:02:03 PM PDT 24 |
Mar 17 01:02:19 PM PDT 24 |
45186800 ps |
| T1255 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.123851375 |
|
|
Mar 17 01:02:04 PM PDT 24 |
Mar 17 01:02:17 PM PDT 24 |
11870800 ps |
| T1256 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4006438329 |
|
|
Mar 17 01:02:28 PM PDT 24 |
Mar 17 01:02:45 PM PDT 24 |
232101800 ps |