Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	171727	1		T1	1		T2	1		T3	1
all_values[1]	171727	1		T1	1		T2	1		T3	1
all_values[2]	171727	1		T1	1		T2	1		T3	1
all_values[3]	171727	1		T1	1		T2	1		T3	1
all_values[4]	171727	1		T1	1		T2	1		T3	1
all_values[5]	171727	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	349259	1		T1	6		T2	6		T3	6
auto[1]	681103	1		T35	4900		T42	6704		T43	86180

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	507044	1		T1	4		T2	4		T3	4
auto[1]	523318	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	171574	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	153	1		T271	5		T272	3		T273	3
all_values[1]	auto[0]	auto[1]	171598	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	129	1		T271	6		T272	1		T273	5
all_values[2]	auto[0]	auto[0]	1485	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	53	1		T271	1		T273	1		T329	1
all_values[2]	auto[1]	auto[0]	170141	1		T35	1225		T42	1676		T43	21545
all_values[2]	auto[1]	auto[1]	48	1		T271	3		T272	2		T273	1
all_values[3]	auto[0]	auto[0]	1443	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	55	1		T271	1		T273	2		T329	1
all_values[3]	auto[1]	auto[0]	50635	1		T35	1225		T42	838		T202	938
all_values[3]	auto[1]	auto[1]	119594	1		T42	838		T43	21545		T44	1978
all_values[4]	auto[0]	auto[0]	1057	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	478	1		T4	1		T6	1		T32	1
all_values[4]	auto[1]	auto[0]	110695	1		T35	1		T42	838		T43	20690
all_values[4]	auto[1]	auto[1]	59497	1		T35	1224		T42	838		T43	855
all_values[5]	auto[0]	auto[0]	1425	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	91	1		T32	1		T23	1		T45	1
all_values[5]	auto[1]	auto[0]	170163	1		T35	1225		T42	1676		T43	21545
all_values[5]	auto[1]	auto[1]	48	1		T331	3		T330	1		T332	2