Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8601 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
1 |
| others[1] |
1036 |
1 |
|
T22 |
8 |
|
T95 |
13 |
|
T57 |
12 |
| others[2] |
1041 |
1 |
|
T22 |
10 |
|
T49 |
1 |
|
T95 |
17 |
| others[3] |
1803 |
1 |
|
T32 |
1 |
|
T22 |
14 |
|
T23 |
2 |
| false |
547 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T22 |
10 |
| true |
1344 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T67 |
13 |
|
T92 |
1 |
|
T68 |
11 |
| others[1] |
219 |
1 |
|
T67 |
5 |
|
T68 |
9 |
|
T244 |
1 |
| others[2] |
227 |
1 |
|
T76 |
1 |
|
T131 |
1 |
|
T168 |
1 |
| others[3] |
370 |
1 |
|
T60 |
1 |
|
T96 |
1 |
|
T82 |
1 |
| false |
105 |
1 |
|
T67 |
3 |
|
T93 |
1 |
|
T68 |
2 |
| true |
13240 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T67 |
6 |
|
T68 |
12 |
|
T83 |
11 |
| others[1] |
214 |
1 |
|
T67 |
11 |
|
T68 |
5 |
|
T83 |
9 |
| others[2] |
189 |
1 |
|
T67 |
11 |
|
T68 |
12 |
|
T105 |
1 |
| others[3] |
369 |
1 |
|
T53 |
1 |
|
T35 |
1 |
|
T67 |
17 |
| false |
106 |
1 |
|
T81 |
1 |
|
T45 |
1 |
|
T67 |
5 |
| true |
13293 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8873 |
1 |
|
T4 |
1 |
|
T22 |
20 |
|
T95 |
21 |
| others[1] |
1242 |
1 |
|
T22 |
22 |
|
T23 |
1 |
|
T95 |
18 |
| others[2] |
1248 |
1 |
|
T4 |
2 |
|
T32 |
1 |
|
T22 |
21 |
| others[3] |
2056 |
1 |
|
T20 |
1 |
|
T8 |
1 |
|
T22 |
30 |
| false |
606 |
1 |
|
T22 |
7 |
|
T95 |
5 |
|
T78 |
6 |
| true |
347 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8820 |
1 |
|
T4 |
2 |
|
T22 |
17 |
|
T95 |
19 |
| others[1] |
1246 |
1 |
|
T22 |
26 |
|
T95 |
16 |
|
T57 |
7 |
| others[2] |
1226 |
1 |
|
T4 |
1 |
|
T22 |
17 |
|
T95 |
12 |
| others[3] |
2112 |
1 |
|
T8 |
1 |
|
T22 |
30 |
|
T34 |
1 |
| false |
631 |
1 |
|
T22 |
10 |
|
T49 |
1 |
|
T95 |
7 |
| true |
337 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T53 |
1 |
|
T67 |
1 |
|
T68 |
4 |
| others[1] |
107 |
1 |
|
T76 |
1 |
|
T67 |
6 |
|
T68 |
8 |
| others[2] |
103 |
1 |
|
T96 |
1 |
|
T53 |
1 |
|
T67 |
3 |
| others[3] |
161 |
1 |
|
T168 |
1 |
|
T67 |
3 |
|
T68 |
5 |
| false |
56 |
1 |
|
T67 |
2 |
|
T68 |
2 |
|
T384 |
1 |
| true |
13829 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T67 |
10 |
|
T68 |
7 |
|
T83 |
6 |
| others[1] |
216 |
1 |
|
T60 |
1 |
|
T76 |
1 |
|
T130 |
1 |
| others[2] |
225 |
1 |
|
T5 |
1 |
|
T131 |
1 |
|
T67 |
12 |
| others[3] |
401 |
1 |
|
T34 |
1 |
|
T96 |
1 |
|
T67 |
16 |
| false |
109 |
1 |
|
T33 |
1 |
|
T35 |
1 |
|
T67 |
2 |
| true |
13190 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8625 |
1 |
|
T2 |
1 |
|
T22 |
5 |
|
T95 |
17 |
| others[1] |
1036 |
1 |
|
T4 |
1 |
|
T22 |
8 |
|
T95 |
17 |
| others[2] |
1023 |
1 |
|
T5 |
1 |
|
T22 |
11 |
|
T49 |
1 |
| others[3] |
1755 |
1 |
|
T4 |
2 |
|
T22 |
23 |
|
T13 |
1 |
| false |
535 |
1 |
|
T22 |
8 |
|
T95 |
9 |
|
T57 |
2 |
| true |
1398 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T34 |
1 |
|
T67 |
5 |
|
T68 |
14 |
| others[1] |
228 |
1 |
|
T67 |
17 |
|
T61 |
1 |
|
T68 |
9 |
| others[2] |
247 |
1 |
|
T47 |
1 |
|
T53 |
1 |
|
T67 |
7 |
| others[3] |
377 |
1 |
|
T60 |
1 |
|
T76 |
1 |
|
T82 |
1 |
| false |
119 |
1 |
|
T168 |
1 |
|
T67 |
9 |
|
T68 |
8 |
| true |
13193 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T67 |
9 |
|
T68 |
13 |
|
T83 |
7 |
| others[1] |
221 |
1 |
|
T67 |
5 |
|
T68 |
11 |
|
T83 |
8 |
| others[2] |
203 |
1 |
|
T53 |
1 |
|
T67 |
9 |
|
T68 |
13 |
| others[3] |
350 |
1 |
|
T81 |
1 |
|
T53 |
1 |
|
T35 |
1 |
| false |
116 |
1 |
|
T67 |
6 |
|
T68 |
1 |
|
T83 |
7 |
| true |
13269 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8861 |
1 |
|
T4 |
2 |
|
T22 |
19 |
|
T95 |
12 |
| others[1] |
1252 |
1 |
|
T22 |
19 |
|
T23 |
1 |
|
T95 |
14 |
| others[2] |
1297 |
1 |
|
T4 |
1 |
|
T22 |
28 |
|
T49 |
1 |
| others[3] |
1995 |
1 |
|
T32 |
1 |
|
T22 |
29 |
|
T95 |
28 |
| false |
614 |
1 |
|
T22 |
5 |
|
T81 |
1 |
|
T95 |
8 |
| true |
353 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T4 |
1 |
|
T22 |
22 |
|
T95 |
14 |
| others[1] |
1242 |
1 |
|
T4 |
1 |
|
T22 |
21 |
|
T13 |
1 |
| others[2] |
1156 |
1 |
|
T22 |
13 |
|
T95 |
16 |
|
T57 |
5 |
| others[3] |
2121 |
1 |
|
T4 |
1 |
|
T22 |
37 |
|
T49 |
1 |
| false |
653 |
1 |
|
T22 |
7 |
|
T95 |
9 |
|
T57 |
4 |
| true |
349 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T81 |
1 |
|
T53 |
1 |
|
T67 |
2 |
| others[1] |
100 |
1 |
|
T67 |
5 |
|
T68 |
6 |
|
T116 |
1 |
| others[2] |
92 |
1 |
|
T67 |
2 |
|
T68 |
4 |
|
T244 |
1 |
| others[3] |
155 |
1 |
|
T96 |
1 |
|
T82 |
1 |
|
T67 |
4 |
| false |
55 |
1 |
|
T53 |
1 |
|
T67 |
2 |
|
T68 |
1 |
| true |
6266 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T34 |
1 |
|
T82 |
1 |
|
T131 |
1 |
| others[1] |
245 |
1 |
|
T5 |
1 |
|
T33 |
1 |
|
T53 |
1 |
| others[2] |
251 |
1 |
|
T60 |
1 |
|
T67 |
8 |
|
T92 |
1 |
| others[3] |
365 |
1 |
|
T130 |
1 |
|
T168 |
1 |
|
T67 |
7 |
| false |
130 |
1 |
|
T47 |
1 |
|
T67 |
9 |
|
T61 |
1 |
| true |
5559 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
993 |
1 |
|
T4 |
1 |
|
T22 |
12 |
|
T95 |
14 |
| others[1] |
1036 |
1 |
|
T4 |
2 |
|
T32 |
1 |
|
T22 |
11 |
| others[2] |
1086 |
1 |
|
T20 |
1 |
|
T32 |
1 |
|
T22 |
9 |
| others[3] |
1774 |
1 |
|
T8 |
1 |
|
T22 |
16 |
|
T13 |
1 |
| false |
519 |
1 |
|
T2 |
1 |
|
T22 |
2 |
|
T95 |
8 |
| true |
1350 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T34 |
1 |
|
T60 |
1 |
|
T131 |
1 |
| others[1] |
220 |
1 |
|
T67 |
11 |
|
T92 |
1 |
|
T61 |
1 |
| others[2] |
197 |
1 |
|
T53 |
1 |
|
T67 |
8 |
|
T61 |
2 |
| others[3] |
403 |
1 |
|
T96 |
1 |
|
T47 |
1 |
|
T67 |
26 |
| false |
126 |
1 |
|
T81 |
1 |
|
T67 |
4 |
|
T61 |
1 |
| true |
5604 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T35 |
1 |
|
T67 |
7 |
|
T68 |
17 |
| others[1] |
218 |
1 |
|
T81 |
1 |
|
T45 |
1 |
|
T67 |
7 |
| others[2] |
208 |
1 |
|
T67 |
8 |
|
T68 |
10 |
|
T105 |
1 |
| others[3] |
358 |
1 |
|
T67 |
17 |
|
T68 |
15 |
|
T83 |
21 |
| false |
102 |
1 |
|
T76 |
1 |
|
T82 |
1 |
|
T67 |
5 |
| true |
5636 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1201 |
1 |
|
T5 |
1 |
|
T22 |
17 |
|
T95 |
19 |
| others[1] |
1246 |
1 |
|
T4 |
1 |
|
T22 |
23 |
|
T23 |
1 |
| others[2] |
1265 |
1 |
|
T4 |
2 |
|
T48 |
1 |
|
T22 |
19 |
| others[3] |
2048 |
1 |
|
T7 |
1 |
|
T32 |
2 |
|
T22 |
36 |
| false |
637 |
1 |
|
T22 |
5 |
|
T95 |
8 |
|
T57 |
6 |
| true |
361 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1162 |
1 |
|
T4 |
1 |
|
T22 |
16 |
|
T95 |
13 |
| others[1] |
1237 |
1 |
|
T4 |
1 |
|
T22 |
15 |
|
T34 |
1 |
| others[2] |
1263 |
1 |
|
T22 |
26 |
|
T81 |
1 |
|
T95 |
12 |
| others[3] |
2118 |
1 |
|
T4 |
1 |
|
T22 |
34 |
|
T13 |
1 |
| false |
649 |
1 |
|
T22 |
9 |
|
T95 |
6 |
|
T57 |
5 |
| true |
329 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T53 |
1 |
|
T168 |
1 |
|
T67 |
9 |
| others[1] |
97 |
1 |
|
T96 |
1 |
|
T67 |
4 |
|
T68 |
3 |
| others[2] |
113 |
1 |
|
T67 |
4 |
|
T68 |
2 |
|
T244 |
1 |
| others[3] |
172 |
1 |
|
T53 |
1 |
|
T67 |
11 |
|
T68 |
7 |
| false |
50 |
1 |
|
T67 |
3 |
|
T68 |
3 |
|
T83 |
2 |
| true |
6212 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T34 |
1 |
|
T67 |
9 |
|
T68 |
14 |
| others[1] |
223 |
1 |
|
T81 |
1 |
|
T82 |
1 |
|
T67 |
13 |
| others[2] |
222 |
1 |
|
T53 |
2 |
|
T67 |
8 |
|
T91 |
1 |
| others[3] |
372 |
1 |
|
T20 |
1 |
|
T130 |
1 |
|
T131 |
1 |
| false |
129 |
1 |
|
T35 |
1 |
|
T67 |
8 |
|
T68 |
6 |
| true |
5575 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1062 |
1 |
|
T4 |
2 |
|
T22 |
9 |
|
T13 |
1 |
| others[1] |
1050 |
1 |
|
T22 |
10 |
|
T95 |
13 |
|
T9 |
1 |
| others[2] |
1049 |
1 |
|
T22 |
7 |
|
T95 |
17 |
|
T57 |
9 |
| others[3] |
1735 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
| false |
534 |
1 |
|
T22 |
4 |
|
T95 |
9 |
|
T57 |
1 |
| true |
1328 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T35 |
1 |
|
T67 |
9 |
|
T68 |
12 |
| others[1] |
235 |
1 |
|
T67 |
10 |
|
T68 |
11 |
|
T244 |
1 |
| others[2] |
174 |
1 |
|
T82 |
1 |
|
T45 |
1 |
|
T53 |
1 |
| others[3] |
371 |
1 |
|
T33 |
1 |
|
T34 |
1 |
|
T47 |
1 |
| false |
126 |
1 |
|
T76 |
1 |
|
T67 |
4 |
|
T92 |
1 |
| true |
5631 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T67 |
10 |
|
T68 |
14 |
|
T244 |
1 |
| others[1] |
210 |
1 |
|
T81 |
1 |
|
T67 |
13 |
|
T68 |
7 |
| others[2] |
219 |
1 |
|
T53 |
2 |
|
T67 |
10 |
|
T68 |
9 |
| others[3] |
380 |
1 |
|
T76 |
1 |
|
T168 |
1 |
|
T67 |
15 |
| false |
117 |
1 |
|
T45 |
1 |
|
T67 |
5 |
|
T68 |
4 |
| true |
5610 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T32 |
1 |
|
T22 |
16 |
|
T95 |
19 |
| others[1] |
1214 |
1 |
|
T4 |
2 |
|
T22 |
18 |
|
T23 |
1 |
| others[2] |
1190 |
1 |
|
T22 |
20 |
|
T49 |
1 |
|
T95 |
10 |
| others[3] |
2118 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T22 |
43 |
| false |
641 |
1 |
|
T22 |
3 |
|
T95 |
9 |
|
T57 |
3 |
| true |
373 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T4 |
1 |
|
T22 |
13 |
|
T34 |
1 |
| others[1] |
1207 |
1 |
|
T4 |
1 |
|
T22 |
29 |
|
T95 |
10 |
| others[2] |
1225 |
1 |
|
T4 |
1 |
|
T22 |
18 |
|
T95 |
13 |
| others[3] |
2066 |
1 |
|
T22 |
31 |
|
T13 |
1 |
|
T49 |
1 |
| false |
662 |
1 |
|
T22 |
9 |
|
T95 |
11 |
|
T9 |
1 |
| true |
345 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T96 |
1 |
|
T67 |
3 |
|
T68 |
2 |
| others[1] |
103 |
1 |
|
T67 |
7 |
|
T68 |
8 |
|
T105 |
1 |
| others[2] |
108 |
1 |
|
T53 |
2 |
|
T67 |
5 |
|
T68 |
5 |
| others[3] |
163 |
1 |
|
T67 |
4 |
|
T68 |
6 |
|
T244 |
1 |
| false |
51 |
1 |
|
T67 |
3 |
|
T83 |
4 |
|
T384 |
1 |
| true |
6231 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T20 |
1 |
|
T46 |
1 |
|
T67 |
12 |
| others[1] |
207 |
1 |
|
T131 |
1 |
|
T67 |
12 |
|
T61 |
1 |
| others[2] |
223 |
1 |
|
T47 |
1 |
|
T67 |
5 |
|
T91 |
1 |
| others[3] |
412 |
1 |
|
T33 |
1 |
|
T81 |
1 |
|
T130 |
1 |
| false |
110 |
1 |
|
T76 |
1 |
|
T67 |
4 |
|
T61 |
2 |
| true |
5572 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1017 |
1 |
|
T22 |
10 |
|
T23 |
2 |
|
T49 |
1 |
| others[1] |
1066 |
1 |
|
T8 |
1 |
|
T22 |
6 |
|
T95 |
17 |
| others[2] |
1087 |
1 |
|
T4 |
1 |
|
T22 |
11 |
|
T95 |
19 |
| others[3] |
1755 |
1 |
|
T4 |
2 |
|
T7 |
1 |
|
T32 |
1 |
| false |
482 |
1 |
|
T32 |
1 |
|
T22 |
3 |
|
T95 |
6 |
| true |
1351 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T47 |
1 |
|
T131 |
1 |
|
T168 |
1 |
| others[1] |
250 |
1 |
|
T76 |
1 |
|
T67 |
9 |
|
T61 |
2 |
| others[2] |
227 |
1 |
|
T82 |
1 |
|
T67 |
14 |
|
T61 |
1 |
| others[3] |
369 |
1 |
|
T33 |
1 |
|
T96 |
1 |
|
T67 |
18 |
| false |
98 |
1 |
|
T34 |
1 |
|
T67 |
4 |
|
T61 |
1 |
| true |
5602 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T81 |
1 |
|
T82 |
1 |
|
T53 |
1 |
| others[1] |
219 |
1 |
|
T67 |
14 |
|
T68 |
11 |
|
T83 |
8 |
| others[2] |
218 |
1 |
|
T67 |
6 |
|
T68 |
10 |
|
T10 |
1 |
| others[3] |
356 |
1 |
|
T67 |
23 |
|
T68 |
16 |
|
T116 |
1 |
| false |
108 |
1 |
|
T45 |
1 |
|
T67 |
4 |
|
T68 |
4 |
| true |
5621 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |