Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1313 |
1 |
|
T4 |
1 |
|
T22 |
20 |
|
T23 |
1 |
| others[1] |
1225 |
1 |
|
T22 |
21 |
|
T95 |
16 |
|
T57 |
9 |
| others[2] |
1207 |
1 |
|
T4 |
1 |
|
T22 |
20 |
|
T95 |
10 |
| others[3] |
2061 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T32 |
1 |
| false |
611 |
1 |
|
T8 |
1 |
|
T22 |
7 |
|
T95 |
9 |
| true |
341 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T3 |
1 |
|
T22 |
15 |
|
T95 |
17 |
| others[1] |
1258 |
1 |
|
T4 |
1 |
|
T22 |
16 |
|
T49 |
1 |
| others[2] |
1162 |
1 |
|
T4 |
1 |
|
T22 |
22 |
|
T95 |
7 |
| others[3] |
2084 |
1 |
|
T4 |
1 |
|
T22 |
35 |
|
T95 |
33 |
| false |
709 |
1 |
|
T22 |
12 |
|
T95 |
7 |
|
T57 |
5 |
| true |
342 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T67 |
1 |
|
T68 |
8 |
|
T83 |
3 |
| others[1] |
105 |
1 |
|
T96 |
1 |
|
T82 |
1 |
|
T67 |
5 |
| others[2] |
100 |
1 |
|
T53 |
1 |
|
T168 |
1 |
|
T67 |
5 |
| others[3] |
167 |
1 |
|
T53 |
1 |
|
T67 |
7 |
|
T68 |
5 |
| false |
59 |
1 |
|
T67 |
2 |
|
T68 |
3 |
|
T83 |
2 |
| true |
6216 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T20 |
1 |
|
T130 |
1 |
|
T131 |
1 |
| others[1] |
224 |
1 |
|
T60 |
1 |
|
T76 |
1 |
|
T67 |
12 |
| others[2] |
230 |
1 |
|
T33 |
1 |
|
T53 |
1 |
|
T67 |
3 |
| others[3] |
377 |
1 |
|
T53 |
1 |
|
T67 |
20 |
|
T61 |
1 |
| false |
113 |
1 |
|
T46 |
1 |
|
T67 |
7 |
|
T61 |
3 |
| true |
5575 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1054 |
1 |
|
T22 |
9 |
|
T33 |
1 |
|
T95 |
15 |
| others[1] |
977 |
1 |
|
T4 |
1 |
|
T22 |
5 |
|
T23 |
1 |
| others[2] |
1032 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T22 |
2 |
| others[3] |
1742 |
1 |
|
T7 |
1 |
|
T48 |
1 |
|
T22 |
20 |
| false |
521 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T22 |
3 |
| true |
1432 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T60 |
1 |
|
T67 |
8 |
|
T68 |
16 |
| others[1] |
230 |
1 |
|
T34 |
1 |
|
T76 |
1 |
|
T131 |
1 |
| others[2] |
195 |
1 |
|
T47 |
1 |
|
T45 |
1 |
|
T67 |
12 |
| others[3] |
381 |
1 |
|
T81 |
1 |
|
T67 |
22 |
|
T92 |
1 |
| false |
122 |
1 |
|
T33 |
1 |
|
T53 |
1 |
|
T67 |
9 |
| true |
5595 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T67 |
13 |
|
T68 |
9 |
|
T83 |
7 |
| others[1] |
198 |
1 |
|
T45 |
1 |
|
T35 |
1 |
|
T67 |
7 |
| others[2] |
204 |
1 |
|
T76 |
1 |
|
T67 |
12 |
|
T68 |
9 |
| others[3] |
372 |
1 |
|
T81 |
1 |
|
T53 |
1 |
|
T67 |
17 |
| false |
116 |
1 |
|
T67 |
6 |
|
T68 |
8 |
|
T83 |
5 |
| true |
5634 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1214 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T22 |
14 |
| others[1] |
1258 |
1 |
|
T22 |
19 |
|
T95 |
12 |
|
T57 |
6 |
| others[2] |
1212 |
1 |
|
T4 |
1 |
|
T22 |
23 |
|
T95 |
17 |
| others[3] |
2054 |
1 |
|
T5 |
1 |
|
T22 |
38 |
|
T49 |
1 |
| false |
659 |
1 |
|
T4 |
1 |
|
T22 |
6 |
|
T23 |
1 |
| true |
361 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T4 |
1 |
|
T22 |
27 |
|
T13 |
1 |
| others[1] |
1297 |
1 |
|
T22 |
18 |
|
T95 |
16 |
|
T57 |
6 |
| others[2] |
1198 |
1 |
|
T4 |
1 |
|
T22 |
20 |
|
T49 |
1 |
| others[3] |
2078 |
1 |
|
T4 |
1 |
|
T22 |
26 |
|
T95 |
23 |
| false |
652 |
1 |
|
T22 |
9 |
|
T95 |
11 |
|
T57 |
2 |
| true |
344 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T53 |
2 |
|
T67 |
3 |
|
T68 |
6 |
| others[1] |
115 |
1 |
|
T67 |
4 |
|
T68 |
3 |
|
T83 |
4 |
| others[2] |
94 |
1 |
|
T67 |
4 |
|
T68 |
1 |
|
T244 |
1 |
| others[3] |
192 |
1 |
|
T67 |
4 |
|
T68 |
6 |
|
T244 |
1 |
| false |
53 |
1 |
|
T96 |
1 |
|
T67 |
1 |
|
T68 |
4 |
| true |
6205 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T81 |
1 |
|
T67 |
10 |
|
T68 |
13 |
| others[1] |
237 |
1 |
|
T5 |
1 |
|
T67 |
8 |
|
T61 |
2 |
| others[2] |
207 |
1 |
|
T47 |
1 |
|
T67 |
6 |
|
T61 |
1 |
| others[3] |
374 |
1 |
|
T33 |
1 |
|
T45 |
1 |
|
T53 |
1 |
| false |
107 |
1 |
|
T131 |
1 |
|
T67 |
3 |
|
T61 |
1 |
| true |
5609 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1096 |
1 |
|
T4 |
1 |
|
T22 |
7 |
|
T23 |
2 |
| others[1] |
1099 |
1 |
|
T2 |
1 |
|
T22 |
15 |
|
T95 |
14 |
| others[2] |
1004 |
1 |
|
T4 |
1 |
|
T32 |
2 |
|
T22 |
8 |
| others[3] |
1672 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T48 |
1 |
| false |
551 |
1 |
|
T22 |
4 |
|
T95 |
11 |
|
T57 |
5 |
| true |
1336 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T45 |
1 |
|
T67 |
5 |
|
T61 |
1 |
| others[1] |
206 |
1 |
|
T76 |
1 |
|
T53 |
1 |
|
T67 |
13 |
| others[2] |
205 |
1 |
|
T34 |
1 |
|
T81 |
1 |
|
T82 |
1 |
| others[3] |
381 |
1 |
|
T67 |
22 |
|
T93 |
1 |
|
T61 |
1 |
| false |
125 |
1 |
|
T67 |
5 |
|
T68 |
7 |
|
T83 |
5 |
| true |
5625 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T35 |
1 |
|
T67 |
9 |
|
T68 |
12 |
| others[1] |
214 |
1 |
|
T53 |
1 |
|
T67 |
7 |
|
T68 |
10 |
| others[2] |
220 |
1 |
|
T168 |
1 |
|
T67 |
6 |
|
T68 |
13 |
| others[3] |
356 |
1 |
|
T81 |
1 |
|
T67 |
12 |
|
T68 |
18 |
| false |
106 |
1 |
|
T67 |
4 |
|
T68 |
2 |
|
T83 |
6 |
| true |
5648 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T48 |
1 |
|
T22 |
25 |
|
T13 |
1 |
| others[1] |
1211 |
1 |
|
T4 |
1 |
|
T22 |
26 |
|
T23 |
1 |
| others[2] |
1189 |
1 |
|
T22 |
23 |
|
T81 |
1 |
|
T95 |
16 |
| others[3] |
2111 |
1 |
|
T4 |
2 |
|
T32 |
1 |
|
T22 |
24 |
| false |
602 |
1 |
|
T22 |
2 |
|
T95 |
3 |
|
T57 |
4 |
| true |
360 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T3 |
1 |
|
T22 |
18 |
|
T95 |
17 |
| others[1] |
1262 |
1 |
|
T4 |
2 |
|
T22 |
23 |
|
T95 |
15 |
| others[2] |
1223 |
1 |
|
T22 |
20 |
|
T95 |
10 |
|
T57 |
9 |
| others[3] |
2029 |
1 |
|
T32 |
1 |
|
T22 |
33 |
|
T95 |
26 |
| false |
663 |
1 |
|
T4 |
1 |
|
T22 |
6 |
|
T49 |
1 |
| true |
328 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T67 |
3 |
|
T68 |
2 |
|
T83 |
1 |
| others[1] |
100 |
1 |
|
T45 |
1 |
|
T67 |
6 |
|
T68 |
2 |
| others[2] |
99 |
1 |
|
T81 |
1 |
|
T96 |
1 |
|
T67 |
2 |
| others[3] |
161 |
1 |
|
T53 |
1 |
|
T67 |
5 |
|
T68 |
8 |
| false |
48 |
1 |
|
T53 |
1 |
|
T67 |
1 |
|
T68 |
2 |
| true |
6252 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T67 |
12 |
|
T61 |
1 |
|
T68 |
6 |
| others[1] |
225 |
1 |
|
T168 |
1 |
|
T67 |
6 |
|
T61 |
1 |
| others[2] |
208 |
1 |
|
T67 |
12 |
|
T61 |
1 |
|
T68 |
10 |
| others[3] |
356 |
1 |
|
T60 |
1 |
|
T47 |
1 |
|
T67 |
13 |
| false |
124 |
1 |
|
T131 |
1 |
|
T35 |
1 |
|
T67 |
5 |
| true |
5610 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1006 |
1 |
|
T4 |
1 |
|
T48 |
1 |
|
T22 |
14 |
| others[1] |
1063 |
1 |
|
T22 |
7 |
|
T34 |
1 |
|
T95 |
14 |
| others[2] |
1090 |
1 |
|
T22 |
13 |
|
T33 |
1 |
|
T95 |
13 |
| others[3] |
1696 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T7 |
1 |
| false |
561 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T22 |
6 |
| true |
1342 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T32 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T96 |
1 |
|
T67 |
9 |
|
T68 |
6 |
| others[1] |
190 |
1 |
|
T60 |
1 |
|
T168 |
1 |
|
T67 |
13 |
| others[2] |
220 |
1 |
|
T81 |
1 |
|
T47 |
1 |
|
T67 |
10 |
| others[3] |
399 |
1 |
|
T82 |
1 |
|
T53 |
1 |
|
T35 |
1 |
| false |
116 |
1 |
|
T45 |
1 |
|
T67 |
7 |
|
T68 |
4 |
| true |
5616 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T67 |
8 |
|
T68 |
10 |
|
T244 |
1 |
| others[1] |
225 |
1 |
|
T96 |
1 |
|
T76 |
1 |
|
T67 |
7 |
| others[2] |
200 |
1 |
|
T67 |
14 |
|
T68 |
12 |
|
T105 |
1 |
| others[3] |
348 |
1 |
|
T67 |
16 |
|
T68 |
13 |
|
T244 |
1 |
| false |
115 |
1 |
|
T67 |
8 |
|
T68 |
7 |
|
T83 |
7 |
| true |
5633 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T22 |
19 |
|
T95 |
16 |
|
T57 |
3 |
| others[1] |
1224 |
1 |
|
T22 |
16 |
|
T95 |
19 |
|
T57 |
8 |
| others[2] |
1195 |
1 |
|
T22 |
20 |
|
T49 |
1 |
|
T95 |
16 |
| others[3] |
2103 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T22 |
30 |
| false |
633 |
1 |
|
T4 |
2 |
|
T32 |
1 |
|
T22 |
15 |
| true |
358 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1283 |
1 |
|
T4 |
1 |
|
T22 |
19 |
|
T95 |
15 |
| others[1] |
1269 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T22 |
16 |
| others[2] |
1214 |
1 |
|
T22 |
23 |
|
T95 |
17 |
|
T57 |
10 |
| others[3] |
2013 |
1 |
|
T3 |
1 |
|
T22 |
34 |
|
T95 |
26 |
| false |
638 |
1 |
|
T4 |
1 |
|
T22 |
8 |
|
T34 |
1 |
| true |
341 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T81 |
1 |
|
T45 |
1 |
|
T67 |
6 |
| others[1] |
95 |
1 |
|
T96 |
1 |
|
T53 |
1 |
|
T67 |
2 |
| others[2] |
115 |
1 |
|
T67 |
5 |
|
T68 |
5 |
|
T83 |
5 |
| others[3] |
184 |
1 |
|
T76 |
1 |
|
T53 |
1 |
|
T67 |
8 |
| false |
46 |
1 |
|
T67 |
2 |
|
T83 |
3 |
|
T37 |
1 |
| true |
6208 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T53 |
1 |
|
T67 |
12 |
|
T61 |
1 |
| others[1] |
234 |
1 |
|
T67 |
9 |
|
T91 |
1 |
|
T68 |
15 |
| others[2] |
227 |
1 |
|
T33 |
1 |
|
T60 |
1 |
|
T82 |
1 |
| others[3] |
391 |
1 |
|
T5 |
1 |
|
T47 |
1 |
|
T53 |
1 |
| false |
122 |
1 |
|
T130 |
1 |
|
T67 |
4 |
|
T61 |
1 |
| true |
5544 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1056 |
1 |
|
T22 |
9 |
|
T23 |
1 |
|
T95 |
17 |
| others[1] |
1011 |
1 |
|
T4 |
1 |
|
T48 |
1 |
|
T22 |
4 |
| others[2] |
1047 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T22 |
12 |
| others[3] |
1761 |
1 |
|
T4 |
2 |
|
T8 |
1 |
|
T22 |
17 |
| false |
530 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T22 |
8 |
| true |
1353 |
1 |
|
T5 |
1 |
|
T32 |
2 |
|
T22 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T35 |
1 |
|
T67 |
11 |
|
T68 |
11 |
| others[1] |
220 |
1 |
|
T82 |
1 |
|
T53 |
1 |
|
T67 |
7 |
| others[2] |
225 |
1 |
|
T45 |
1 |
|
T67 |
9 |
|
T68 |
13 |
| others[3] |
387 |
1 |
|
T60 |
1 |
|
T53 |
1 |
|
T67 |
17 |
| false |
109 |
1 |
|
T67 |
6 |
|
T68 |
3 |
|
T83 |
3 |
| true |
5576 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
195 |
1 |
|
T67 |
12 |
|
T68 |
4 |
|
T244 |
1 |
| others[1] |
219 |
1 |
|
T76 |
1 |
|
T67 |
10 |
|
T68 |
9 |
| others[2] |
215 |
1 |
|
T96 |
1 |
|
T67 |
6 |
|
T68 |
11 |
| others[3] |
345 |
1 |
|
T45 |
1 |
|
T168 |
1 |
|
T67 |
16 |
| false |
95 |
1 |
|
T67 |
7 |
|
T68 |
5 |
|
T83 |
5 |
| true |
5689 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1199 |
1 |
|
T4 |
1 |
|
T22 |
21 |
|
T95 |
16 |
| others[1] |
1252 |
1 |
|
T3 |
1 |
|
T22 |
23 |
|
T23 |
1 |
| others[2] |
1306 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T22 |
26 |
| others[3] |
2022 |
1 |
|
T4 |
1 |
|
T22 |
22 |
|
T49 |
1 |
| false |
605 |
1 |
|
T22 |
8 |
|
T95 |
6 |
|
T57 |
3 |
| true |
374 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T4 |
1 |
|
T22 |
24 |
|
T95 |
18 |
| others[1] |
1242 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T48 |
1 |
| others[2] |
1256 |
1 |
|
T4 |
1 |
|
T22 |
10 |
|
T95 |
17 |
| others[3] |
2015 |
1 |
|
T22 |
33 |
|
T49 |
1 |
|
T95 |
23 |
| false |
690 |
1 |
|
T22 |
15 |
|
T95 |
9 |
|
T57 |
2 |
| true |
332 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T53 |
1 |
|
T67 |
5 |
|
T68 |
7 |
| others[1] |
110 |
1 |
|
T53 |
1 |
|
T67 |
7 |
|
T68 |
3 |
| others[2] |
102 |
1 |
|
T96 |
1 |
|
T67 |
2 |
|
T68 |
1 |
| others[3] |
178 |
1 |
|
T67 |
8 |
|
T68 |
7 |
|
T83 |
6 |
| false |
57 |
1 |
|
T67 |
6 |
|
T68 |
4 |
|
T83 |
2 |
| true |
6205 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |