Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T53 |
1 |
|
T168 |
1 |
|
T67 |
8 |
| others[1] |
236 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T67 |
5 |
| others[2] |
234 |
1 |
|
T20 |
1 |
|
T34 |
1 |
|
T81 |
1 |
| others[3] |
392 |
1 |
|
T67 |
18 |
|
T61 |
1 |
|
T68 |
17 |
| false |
134 |
1 |
|
T47 |
1 |
|
T35 |
1 |
|
T67 |
6 |
| true |
5549 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1094 |
1 |
|
T5 |
1 |
|
T22 |
7 |
|
T95 |
16 |
| others[1] |
974 |
1 |
|
T22 |
13 |
|
T23 |
1 |
|
T95 |
16 |
| others[2] |
1050 |
1 |
|
T22 |
3 |
|
T33 |
1 |
|
T95 |
17 |
| others[3] |
1701 |
1 |
|
T4 |
2 |
|
T32 |
1 |
|
T48 |
1 |
| false |
540 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T32 |
1 |
| true |
1399 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T67 |
12 |
|
T68 |
10 |
|
T83 |
16 |
| others[1] |
221 |
1 |
|
T96 |
1 |
|
T76 |
1 |
|
T67 |
12 |
| others[2] |
218 |
1 |
|
T33 |
1 |
|
T168 |
1 |
|
T67 |
10 |
| others[3] |
374 |
1 |
|
T60 |
1 |
|
T47 |
1 |
|
T53 |
1 |
| false |
110 |
1 |
|
T82 |
1 |
|
T53 |
1 |
|
T67 |
4 |
| true |
5597 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T67 |
11 |
| others[1] |
229 |
1 |
|
T67 |
13 |
|
T68 |
10 |
|
T116 |
1 |
| others[2] |
214 |
1 |
|
T67 |
8 |
|
T68 |
11 |
|
T83 |
15 |
| others[3] |
352 |
1 |
|
T81 |
1 |
|
T67 |
19 |
|
T68 |
14 |
| false |
122 |
1 |
|
T67 |
3 |
|
T68 |
3 |
|
T83 |
12 |
| true |
5643 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T22 |
19 |
| others[1] |
1248 |
1 |
|
T4 |
2 |
|
T32 |
1 |
|
T22 |
22 |
| others[2] |
1222 |
1 |
|
T22 |
16 |
|
T49 |
1 |
|
T95 |
18 |
| others[3] |
2060 |
1 |
|
T3 |
1 |
|
T22 |
27 |
|
T34 |
1 |
| false |
639 |
1 |
|
T22 |
16 |
|
T95 |
6 |
|
T9 |
1 |
| true |
360 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T22 |
16 |
|
T49 |
1 |
|
T95 |
14 |
| others[1] |
1225 |
1 |
|
T22 |
18 |
|
T95 |
17 |
|
T9 |
1 |
| others[2] |
1235 |
1 |
|
T4 |
2 |
|
T22 |
26 |
|
T95 |
15 |
| others[3] |
2103 |
1 |
|
T4 |
1 |
|
T22 |
33 |
|
T95 |
26 |
| false |
634 |
1 |
|
T22 |
7 |
|
T95 |
7 |
|
T57 |
3 |
| true |
343 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T67 |
3 |
|
T68 |
5 |
|
T105 |
1 |
| others[1] |
97 |
1 |
|
T67 |
5 |
|
T68 |
2 |
|
T83 |
8 |
| others[2] |
104 |
1 |
|
T96 |
1 |
|
T35 |
1 |
|
T67 |
3 |
| others[3] |
167 |
1 |
|
T53 |
2 |
|
T67 |
4 |
|
T68 |
6 |
| false |
41 |
1 |
|
T67 |
1 |
|
T68 |
1 |
|
T83 |
3 |
| true |
6243 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T96 |
1 |
|
T67 |
11 |
|
T93 |
1 |
| others[1] |
236 |
1 |
|
T5 |
1 |
|
T168 |
1 |
|
T67 |
17 |
| others[2] |
202 |
1 |
|
T130 |
1 |
|
T45 |
1 |
|
T67 |
9 |
| others[3] |
383 |
1 |
|
T20 |
1 |
|
T33 |
1 |
|
T81 |
1 |
| false |
106 |
1 |
|
T67 |
3 |
|
T92 |
1 |
|
T61 |
1 |
| true |
5629 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1016 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| others[1] |
1069 |
1 |
|
T22 |
10 |
|
T81 |
1 |
|
T95 |
16 |
| others[2] |
1011 |
1 |
|
T4 |
1 |
|
T22 |
8 |
|
T33 |
1 |
| others[3] |
1732 |
1 |
|
T4 |
1 |
|
T22 |
13 |
|
T95 |
29 |
| false |
536 |
1 |
|
T22 |
3 |
|
T95 |
6 |
|
T57 |
8 |
| true |
1394 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T53 |
1 |
|
T67 |
6 |
|
T68 |
16 |
| others[1] |
225 |
1 |
|
T131 |
1 |
|
T67 |
6 |
|
T68 |
9 |
| others[2] |
210 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T67 |
14 |
| others[3] |
373 |
1 |
|
T33 |
1 |
|
T76 |
1 |
|
T67 |
21 |
| false |
121 |
1 |
|
T82 |
1 |
|
T67 |
7 |
|
T68 |
2 |
| true |
5616 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T67 |
13 |
|
T68 |
8 |
|
T10 |
1 |
| others[1] |
252 |
1 |
|
T96 |
1 |
|
T67 |
14 |
|
T68 |
7 |
| others[2] |
218 |
1 |
|
T67 |
12 |
|
T68 |
14 |
|
T83 |
11 |
| others[3] |
378 |
1 |
|
T53 |
1 |
|
T67 |
18 |
|
T68 |
18 |
| false |
85 |
1 |
|
T76 |
1 |
|
T67 |
3 |
|
T68 |
3 |
| true |
5622 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T22 |
16 |
| others[1] |
1275 |
1 |
|
T4 |
2 |
|
T22 |
18 |
|
T49 |
1 |
| others[2] |
1221 |
1 |
|
T22 |
23 |
|
T23 |
1 |
|
T95 |
17 |
| others[3] |
2001 |
1 |
|
T22 |
34 |
|
T95 |
32 |
|
T57 |
13 |
| false |
637 |
1 |
|
T22 |
9 |
|
T95 |
3 |
|
T57 |
4 |
| true |
372 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T4 |
2 |
|
T22 |
17 |
|
T95 |
16 |
| others[1] |
1237 |
1 |
|
T22 |
24 |
|
T34 |
1 |
|
T95 |
6 |
| others[2] |
1251 |
1 |
|
T8 |
1 |
|
T22 |
17 |
|
T49 |
1 |
| others[3] |
2036 |
1 |
|
T22 |
34 |
|
T95 |
30 |
|
T9 |
1 |
| false |
635 |
1 |
|
T4 |
1 |
|
T22 |
8 |
|
T95 |
6 |
| true |
338 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
83 |
1 |
|
T67 |
4 |
|
T68 |
4 |
|
T244 |
1 |
| others[1] |
104 |
1 |
|
T53 |
1 |
|
T67 |
5 |
|
T68 |
5 |
| others[2] |
104 |
1 |
|
T82 |
1 |
|
T67 |
5 |
|
T68 |
6 |
| others[3] |
160 |
1 |
|
T81 |
1 |
|
T96 |
1 |
|
T53 |
1 |
| false |
58 |
1 |
|
T68 |
2 |
|
T105 |
1 |
|
T83 |
5 |
| true |
6249 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T33 |
1 |
|
T67 |
9 |
|
T68 |
11 |
| others[1] |
231 |
1 |
|
T34 |
1 |
|
T67 |
11 |
|
T68 |
11 |
| others[2] |
229 |
1 |
|
T20 |
1 |
|
T60 |
1 |
|
T67 |
13 |
| others[3] |
381 |
1 |
|
T67 |
18 |
|
T68 |
16 |
|
T115 |
1 |
| false |
113 |
1 |
|
T67 |
8 |
|
T68 |
7 |
|
T244 |
1 |
| true |
5580 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1039 |
1 |
|
T4 |
1 |
|
T22 |
10 |
|
T95 |
18 |
| others[1] |
1025 |
1 |
|
T7 |
1 |
|
T32 |
1 |
|
T22 |
4 |
| others[2] |
1029 |
1 |
|
T4 |
1 |
|
T22 |
11 |
|
T95 |
14 |
| others[3] |
1752 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T32 |
1 |
| false |
565 |
1 |
|
T4 |
1 |
|
T22 |
3 |
|
T95 |
7 |
| true |
1348 |
1 |
|
T5 |
1 |
|
T20 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T34 |
1 |
|
T76 |
1 |
|
T47 |
1 |
| others[1] |
206 |
1 |
|
T168 |
1 |
|
T67 |
6 |
|
T68 |
10 |
| others[2] |
218 |
1 |
|
T81 |
1 |
|
T67 |
8 |
|
T68 |
14 |
| others[3] |
379 |
1 |
|
T67 |
18 |
|
T92 |
1 |
|
T68 |
11 |
| false |
102 |
1 |
|
T53 |
1 |
|
T35 |
1 |
|
T67 |
3 |
| true |
5626 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T45 |
1 |
|
T67 |
8 |
|
T68 |
9 |
| others[1] |
199 |
1 |
|
T53 |
1 |
|
T67 |
12 |
|
T68 |
9 |
| others[2] |
231 |
1 |
|
T53 |
1 |
|
T168 |
1 |
|
T67 |
6 |
| others[3] |
364 |
1 |
|
T67 |
20 |
|
T68 |
20 |
|
T10 |
2 |
| false |
122 |
1 |
|
T67 |
5 |
|
T68 |
6 |
|
T83 |
7 |
| true |
5636 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T4 |
2 |
|
T22 |
24 |
|
T95 |
14 |
| others[1] |
1211 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T22 |
13 |
| others[2] |
1187 |
1 |
|
T22 |
24 |
|
T81 |
1 |
|
T95 |
16 |
| others[3] |
2108 |
1 |
|
T3 |
1 |
|
T22 |
33 |
|
T23 |
1 |
| false |
620 |
1 |
|
T22 |
6 |
|
T95 |
7 |
|
T57 |
2 |
| true |
366 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1177 |
1 |
|
T22 |
22 |
|
T34 |
1 |
|
T95 |
9 |
| others[1] |
1281 |
1 |
|
T8 |
1 |
|
T22 |
19 |
|
T95 |
11 |
| others[2] |
1253 |
1 |
|
T4 |
1 |
|
T22 |
22 |
|
T49 |
1 |
| others[3] |
2074 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T22 |
28 |
| false |
637 |
1 |
|
T22 |
9 |
|
T95 |
7 |
|
T57 |
2 |
| true |
336 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T35 |
1 |
|
T67 |
4 |
|
T68 |
1 |
| others[1] |
94 |
1 |
|
T53 |
2 |
|
T67 |
7 |
|
T68 |
2 |
| others[2] |
90 |
1 |
|
T67 |
2 |
|
T68 |
2 |
|
T83 |
5 |
| others[3] |
177 |
1 |
|
T96 |
1 |
|
T45 |
1 |
|
T67 |
5 |
| false |
56 |
1 |
|
T67 |
1 |
|
T68 |
2 |
|
T83 |
2 |
| true |
6246 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T67 |
10 |
|
T91 |
1 |
|
T68 |
8 |
| others[1] |
234 |
1 |
|
T67 |
7 |
|
T93 |
1 |
|
T61 |
1 |
| others[2] |
227 |
1 |
|
T33 |
1 |
|
T34 |
1 |
|
T82 |
1 |
| others[3] |
358 |
1 |
|
T81 |
1 |
|
T46 |
1 |
|
T130 |
1 |
| false |
119 |
1 |
|
T67 |
2 |
|
T92 |
1 |
|
T68 |
4 |
| true |
5592 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1047 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T22 |
10 |
| others[1] |
1016 |
1 |
|
T32 |
2 |
|
T22 |
11 |
|
T23 |
2 |
| others[2] |
1069 |
1 |
|
T22 |
5 |
|
T13 |
1 |
|
T95 |
15 |
| others[3] |
1736 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T22 |
19 |
| false |
543 |
1 |
|
T22 |
7 |
|
T95 |
5 |
|
T57 |
7 |
| true |
1347 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T60 |
1 |
|
T96 |
1 |
|
T67 |
8 |
| others[1] |
211 |
1 |
|
T81 |
1 |
|
T45 |
1 |
|
T53 |
2 |
| others[2] |
203 |
1 |
|
T67 |
10 |
|
T61 |
1 |
|
T68 |
5 |
| others[3] |
397 |
1 |
|
T33 |
1 |
|
T34 |
1 |
|
T131 |
1 |
| false |
110 |
1 |
|
T67 |
6 |
|
T61 |
1 |
|
T68 |
6 |
| true |
5603 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
194 |
1 |
|
T53 |
1 |
|
T67 |
6 |
|
T68 |
9 |
| others[1] |
226 |
1 |
|
T67 |
4 |
|
T68 |
7 |
|
T83 |
8 |
| others[2] |
207 |
1 |
|
T53 |
1 |
|
T35 |
1 |
|
T67 |
15 |
| others[3] |
358 |
1 |
|
T168 |
1 |
|
T67 |
23 |
|
T68 |
17 |
| false |
102 |
1 |
|
T76 |
1 |
|
T67 |
4 |
|
T68 |
5 |
| true |
5671 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T22 |
20 |
| others[1] |
1238 |
1 |
|
T4 |
1 |
|
T48 |
1 |
|
T22 |
15 |
| others[2] |
1267 |
1 |
|
T22 |
14 |
|
T95 |
15 |
|
T57 |
7 |
| others[3] |
2024 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T22 |
33 |
| false |
652 |
1 |
|
T22 |
18 |
|
T95 |
9 |
|
T57 |
4 |
| true |
354 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T8 |
1 |
|
T22 |
18 |
|
T95 |
13 |
| others[1] |
1243 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| others[2] |
1234 |
1 |
|
T4 |
1 |
|
T22 |
21 |
|
T95 |
20 |
| others[3] |
2027 |
1 |
|
T22 |
24 |
|
T49 |
1 |
|
T95 |
22 |
| false |
644 |
1 |
|
T4 |
1 |
|
T22 |
10 |
|
T95 |
8 |
| true |
347 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T32 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T96 |
1 |
|
T67 |
3 |
|
T68 |
4 |
| others[1] |
101 |
1 |
|
T53 |
1 |
|
T67 |
2 |
|
T68 |
2 |
| others[2] |
79 |
1 |
|
T67 |
1 |
|
T68 |
2 |
|
T83 |
1 |
| others[3] |
175 |
1 |
|
T53 |
1 |
|
T67 |
4 |
|
T68 |
5 |
| false |
61 |
1 |
|
T67 |
4 |
|
T68 |
4 |
|
T83 |
3 |
| true |
6233 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T33 |
1 |
|
T81 |
1 |
|
T60 |
1 |
| others[1] |
233 |
1 |
|
T46 |
1 |
|
T76 |
1 |
|
T67 |
11 |
| others[2] |
216 |
1 |
|
T47 |
1 |
|
T67 |
11 |
|
T92 |
1 |
| others[3] |
395 |
1 |
|
T168 |
1 |
|
T67 |
10 |
|
T93 |
1 |
| false |
125 |
1 |
|
T20 |
1 |
|
T67 |
6 |
|
T68 |
4 |
| true |
5584 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1062 |
1 |
|
T4 |
1 |
|
T22 |
10 |
|
T95 |
11 |
| others[1] |
1034 |
1 |
|
T22 |
7 |
|
T33 |
1 |
|
T95 |
16 |
| others[2] |
1051 |
1 |
|
T4 |
1 |
|
T22 |
10 |
|
T49 |
1 |
| others[3] |
1696 |
1 |
|
T4 |
1 |
|
T22 |
14 |
|
T95 |
30 |
| false |
591 |
1 |
|
T8 |
1 |
|
T22 |
4 |
|
T95 |
7 |
| true |
1324 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T67 |
13 |
|
T68 |
10 |
|
T244 |
1 |
| others[1] |
218 |
1 |
|
T67 |
7 |
|
T68 |
10 |
|
T105 |
1 |
| others[2] |
226 |
1 |
|
T45 |
1 |
|
T67 |
14 |
|
T68 |
8 |
| others[3] |
334 |
1 |
|
T53 |
1 |
|
T67 |
17 |
|
T93 |
1 |
| false |
118 |
1 |
|
T96 |
1 |
|
T35 |
1 |
|
T67 |
10 |
| true |
5644 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |