Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
200 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T67 |
8 |
| others[1] |
228 |
1 |
|
T67 |
1 |
|
T68 |
14 |
|
T83 |
13 |
| others[2] |
209 |
1 |
|
T81 |
1 |
|
T76 |
1 |
|
T67 |
12 |
| others[3] |
377 |
1 |
|
T67 |
15 |
|
T68 |
20 |
|
T83 |
14 |
| false |
114 |
1 |
|
T168 |
1 |
|
T68 |
4 |
|
T116 |
1 |
| true |
5630 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T32 |
1 |
|
T22 |
14 |
|
T95 |
16 |
| others[1] |
1241 |
1 |
|
T4 |
3 |
|
T7 |
1 |
|
T22 |
21 |
| others[2] |
1182 |
1 |
|
T22 |
21 |
|
T95 |
15 |
|
T57 |
4 |
| others[3] |
2075 |
1 |
|
T22 |
35 |
|
T23 |
1 |
|
T49 |
1 |
| false |
678 |
1 |
|
T22 |
9 |
|
T95 |
13 |
|
T57 |
5 |
| true |
369 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T22 |
18 |
|
T49 |
1 |
|
T95 |
19 |
| others[1] |
1281 |
1 |
|
T22 |
17 |
|
T95 |
18 |
|
T57 |
13 |
| others[2] |
1276 |
1 |
|
T4 |
2 |
|
T22 |
22 |
|
T95 |
14 |
| others[3] |
2032 |
1 |
|
T22 |
33 |
|
T95 |
17 |
|
T57 |
12 |
| false |
622 |
1 |
|
T4 |
1 |
|
T22 |
10 |
|
T95 |
11 |
| true |
338 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T96 |
1 |
|
T53 |
1 |
|
T67 |
5 |
| others[1] |
110 |
1 |
|
T67 |
5 |
|
T68 |
5 |
|
T83 |
9 |
| others[2] |
119 |
1 |
|
T67 |
7 |
|
T68 |
6 |
|
T244 |
1 |
| others[3] |
164 |
1 |
|
T76 |
1 |
|
T53 |
1 |
|
T67 |
6 |
| false |
52 |
1 |
|
T67 |
2 |
|
T68 |
2 |
|
T83 |
1 |
| true |
6219 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T33 |
1 |
|
T81 |
1 |
|
T82 |
1 |
| others[1] |
226 |
1 |
|
T46 |
1 |
|
T76 |
1 |
|
T47 |
1 |
| others[2] |
224 |
1 |
|
T20 |
1 |
|
T53 |
2 |
|
T35 |
1 |
| others[3] |
380 |
1 |
|
T5 |
1 |
|
T60 |
1 |
|
T67 |
21 |
| false |
103 |
1 |
|
T67 |
4 |
|
T10 |
1 |
|
T83 |
4 |
| true |
5574 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1031 |
1 |
|
T22 |
14 |
|
T34 |
1 |
|
T95 |
19 |
| others[1] |
1043 |
1 |
|
T22 |
11 |
|
T49 |
1 |
|
T95 |
15 |
| others[2] |
1039 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T22 |
7 |
| others[3] |
1742 |
1 |
|
T20 |
1 |
|
T8 |
1 |
|
T22 |
18 |
| false |
579 |
1 |
|
T4 |
3 |
|
T22 |
7 |
|
T95 |
7 |
| true |
1324 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T32 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T45 |
1 |
|
T67 |
8 |
|
T68 |
8 |
| others[1] |
197 |
1 |
|
T33 |
1 |
|
T60 |
1 |
|
T76 |
1 |
| others[2] |
247 |
1 |
|
T81 |
1 |
|
T82 |
1 |
|
T67 |
12 |
| others[3] |
352 |
1 |
|
T67 |
13 |
|
T92 |
1 |
|
T68 |
10 |
| false |
122 |
1 |
|
T67 |
6 |
|
T68 |
7 |
|
T83 |
7 |
| true |
5608 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T67 |
7 |
|
T68 |
8 |
|
T10 |
2 |
| others[1] |
238 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T35 |
1 |
| others[2] |
191 |
1 |
|
T96 |
1 |
|
T67 |
10 |
|
T68 |
7 |
| others[3] |
340 |
1 |
|
T67 |
20 |
|
T68 |
22 |
|
T244 |
1 |
| false |
110 |
1 |
|
T67 |
8 |
|
T68 |
3 |
|
T244 |
1 |
| true |
5661 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T22 |
20 |
|
T95 |
16 |
|
T9 |
1 |
| others[1] |
1183 |
1 |
|
T22 |
17 |
|
T23 |
1 |
|
T95 |
15 |
| others[2] |
1256 |
1 |
|
T32 |
1 |
|
T22 |
19 |
|
T49 |
1 |
| others[3] |
2106 |
1 |
|
T4 |
3 |
|
T22 |
33 |
|
T34 |
1 |
| false |
639 |
1 |
|
T22 |
11 |
|
T95 |
6 |
|
T57 |
3 |
| true |
357 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T22 |
21 |
|
T95 |
17 |
|
T57 |
7 |
| others[1] |
1252 |
1 |
|
T32 |
1 |
|
T22 |
13 |
|
T49 |
1 |
| others[2] |
1206 |
1 |
|
T5 |
1 |
|
T22 |
15 |
|
T95 |
14 |
| others[3] |
2101 |
1 |
|
T4 |
1 |
|
T22 |
42 |
|
T81 |
1 |
| false |
641 |
1 |
|
T4 |
2 |
|
T22 |
9 |
|
T95 |
7 |
| true |
343 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T67 |
3 |
|
T68 |
4 |
|
T83 |
5 |
| others[1] |
103 |
1 |
|
T96 |
1 |
|
T67 |
1 |
|
T68 |
5 |
| others[2] |
109 |
1 |
|
T53 |
1 |
|
T67 |
5 |
|
T68 |
5 |
| others[3] |
172 |
1 |
|
T53 |
1 |
|
T67 |
8 |
|
T68 |
7 |
| false |
50 |
1 |
|
T168 |
1 |
|
T67 |
1 |
|
T83 |
4 |
| true |
6232 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T5 |
1 |
|
T33 |
1 |
|
T67 |
9 |
| others[1] |
222 |
1 |
|
T60 |
1 |
|
T53 |
1 |
|
T67 |
9 |
| others[2] |
222 |
1 |
|
T82 |
1 |
|
T67 |
11 |
|
T91 |
1 |
| others[3] |
369 |
1 |
|
T20 |
1 |
|
T46 |
1 |
|
T131 |
1 |
| false |
119 |
1 |
|
T76 |
1 |
|
T168 |
1 |
|
T67 |
4 |
| true |
5604 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1031 |
1 |
|
T22 |
10 |
|
T13 |
1 |
|
T95 |
11 |
| others[1] |
1036 |
1 |
|
T22 |
8 |
|
T81 |
1 |
|
T95 |
19 |
| others[2] |
1049 |
1 |
|
T22 |
10 |
|
T95 |
13 |
|
T57 |
2 |
| others[3] |
1714 |
1 |
|
T4 |
3 |
|
T22 |
14 |
|
T33 |
1 |
| false |
542 |
1 |
|
T22 |
7 |
|
T95 |
7 |
|
T57 |
3 |
| true |
1386 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T67 |
15 |
|
T68 |
7 |
|
T83 |
6 |
| others[1] |
223 |
1 |
|
T34 |
1 |
|
T53 |
1 |
|
T67 |
7 |
| others[2] |
249 |
1 |
|
T33 |
1 |
|
T67 |
12 |
|
T68 |
11 |
| others[3] |
347 |
1 |
|
T82 |
1 |
|
T45 |
1 |
|
T67 |
16 |
| false |
128 |
1 |
|
T67 |
6 |
|
T68 |
12 |
|
T105 |
1 |
| true |
5602 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T67 |
9 |
|
T68 |
14 |
|
T10 |
1 |
| others[1] |
216 |
1 |
|
T76 |
1 |
|
T53 |
1 |
|
T67 |
7 |
| others[2] |
201 |
1 |
|
T67 |
10 |
|
T68 |
8 |
|
T10 |
2 |
| others[3] |
358 |
1 |
|
T81 |
1 |
|
T82 |
1 |
|
T168 |
1 |
| false |
113 |
1 |
|
T67 |
8 |
|
T68 |
5 |
|
T10 |
1 |
| true |
5666 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1191 |
1 |
|
T4 |
1 |
|
T22 |
18 |
|
T95 |
10 |
| others[1] |
1240 |
1 |
|
T4 |
2 |
|
T22 |
16 |
|
T95 |
21 |
| others[2] |
1179 |
1 |
|
T32 |
1 |
|
T22 |
19 |
|
T49 |
1 |
| others[3] |
2128 |
1 |
|
T22 |
40 |
|
T23 |
1 |
|
T95 |
22 |
| false |
655 |
1 |
|
T22 |
7 |
|
T95 |
8 |
|
T57 |
5 |
| true |
365 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T4 |
1 |
|
T22 |
20 |
|
T34 |
1 |
| others[1] |
1209 |
1 |
|
T5 |
1 |
|
T22 |
19 |
|
T95 |
17 |
| others[2] |
1243 |
1 |
|
T22 |
20 |
|
T49 |
1 |
|
T95 |
17 |
| others[3] |
2066 |
1 |
|
T4 |
2 |
|
T22 |
29 |
|
T95 |
27 |
| false |
653 |
1 |
|
T22 |
12 |
|
T95 |
5 |
|
T57 |
3 |
| true |
336 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T168 |
1 |
|
T67 |
4 |
|
T68 |
3 |
| others[1] |
101 |
1 |
|
T35 |
1 |
|
T67 |
3 |
|
T68 |
4 |
| others[2] |
123 |
1 |
|
T67 |
6 |
|
T68 |
3 |
|
T83 |
6 |
| others[3] |
155 |
1 |
|
T81 |
1 |
|
T96 |
1 |
|
T82 |
1 |
| false |
62 |
1 |
|
T53 |
1 |
|
T67 |
3 |
|
T68 |
2 |
| true |
6215 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T33 |
1 |
|
T47 |
1 |
|
T82 |
1 |
| others[1] |
246 |
1 |
|
T96 |
1 |
|
T67 |
16 |
|
T61 |
2 |
| others[2] |
227 |
1 |
|
T67 |
11 |
|
T61 |
1 |
|
T68 |
9 |
| others[3] |
383 |
1 |
|
T60 |
1 |
|
T45 |
1 |
|
T67 |
19 |
| false |
108 |
1 |
|
T81 |
1 |
|
T67 |
2 |
|
T68 |
4 |
| true |
5560 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1099 |
1 |
|
T4 |
1 |
|
T22 |
10 |
|
T23 |
1 |
| others[1] |
1051 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T22 |
6 |
| others[2] |
1048 |
1 |
|
T4 |
1 |
|
T22 |
10 |
|
T23 |
1 |
| others[3] |
1697 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T48 |
1 |
| false |
525 |
1 |
|
T22 |
7 |
|
T95 |
8 |
|
T57 |
2 |
| true |
1338 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
262 |
1 |
|
T82 |
1 |
|
T131 |
1 |
|
T53 |
1 |
| others[1] |
231 |
1 |
|
T47 |
1 |
|
T67 |
11 |
|
T61 |
2 |
| others[2] |
207 |
1 |
|
T34 |
1 |
|
T67 |
6 |
|
T93 |
1 |
| others[3] |
366 |
1 |
|
T53 |
1 |
|
T67 |
19 |
|
T61 |
2 |
| false |
96 |
1 |
|
T68 |
6 |
|
T83 |
4 |
|
T385 |
1 |
| true |
5596 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T35 |
1 |
|
T67 |
11 |
|
T68 |
14 |
| others[1] |
223 |
1 |
|
T67 |
4 |
|
T68 |
10 |
|
T83 |
13 |
| others[2] |
195 |
1 |
|
T53 |
1 |
|
T67 |
7 |
|
T68 |
9 |
| others[3] |
351 |
1 |
|
T96 |
1 |
|
T67 |
26 |
|
T68 |
16 |
| false |
118 |
1 |
|
T67 |
8 |
|
T68 |
4 |
|
T83 |
5 |
| true |
5644 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T3 |
1 |
|
T7 |
1 |
|
T22 |
14 |
| others[1] |
1251 |
1 |
|
T4 |
1 |
|
T22 |
26 |
|
T95 |
15 |
| others[2] |
1319 |
1 |
|
T32 |
1 |
|
T22 |
22 |
|
T23 |
1 |
| others[3] |
2043 |
1 |
|
T4 |
2 |
|
T22 |
29 |
|
T49 |
1 |
| false |
569 |
1 |
|
T22 |
9 |
|
T95 |
6 |
|
T57 |
6 |
| true |
354 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T4 |
1 |
|
T22 |
24 |
|
T49 |
1 |
| others[1] |
1226 |
1 |
|
T4 |
2 |
|
T22 |
16 |
|
T95 |
20 |
| others[2] |
1176 |
1 |
|
T22 |
24 |
|
T34 |
1 |
|
T95 |
10 |
| others[3] |
2109 |
1 |
|
T22 |
28 |
|
T95 |
28 |
|
T57 |
15 |
| false |
654 |
1 |
|
T22 |
8 |
|
T95 |
10 |
|
T57 |
1 |
| true |
347 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T67 |
7 |
|
T68 |
3 |
|
T116 |
1 |
| others[1] |
98 |
1 |
|
T67 |
1 |
|
T68 |
2 |
|
T244 |
1 |
| others[2] |
114 |
1 |
|
T67 |
4 |
|
T68 |
2 |
|
T244 |
1 |
| others[3] |
165 |
1 |
|
T96 |
1 |
|
T76 |
1 |
|
T53 |
2 |
| false |
55 |
1 |
|
T68 |
2 |
|
T83 |
3 |
|
T108 |
2 |
| true |
6224 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T34 |
1 |
|
T131 |
1 |
|
T67 |
11 |
| others[1] |
234 |
1 |
|
T130 |
1 |
|
T67 |
12 |
|
T68 |
12 |
| others[2] |
223 |
1 |
|
T20 |
1 |
|
T33 |
1 |
|
T76 |
1 |
| others[3] |
379 |
1 |
|
T81 |
1 |
|
T96 |
1 |
|
T47 |
1 |
| false |
116 |
1 |
|
T67 |
7 |
|
T68 |
3 |
|
T244 |
1 |
| true |
5577 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1060 |
1 |
|
T22 |
17 |
|
T95 |
11 |
|
T9 |
1 |
| others[1] |
1024 |
1 |
|
T22 |
9 |
|
T95 |
16 |
|
T57 |
4 |
| others[2] |
1034 |
1 |
|
T4 |
3 |
|
T32 |
2 |
|
T22 |
12 |
| others[3] |
1736 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T7 |
1 |
| false |
537 |
1 |
|
T22 |
6 |
|
T95 |
15 |
|
T57 |
5 |
| true |
1367 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T67 |
14 |
|
T68 |
9 |
|
T244 |
1 |
| others[1] |
231 |
1 |
|
T82 |
1 |
|
T53 |
1 |
|
T67 |
7 |
| others[2] |
222 |
1 |
|
T47 |
1 |
|
T67 |
14 |
|
T93 |
1 |
| others[3] |
361 |
1 |
|
T60 |
1 |
|
T67 |
12 |
|
T68 |
15 |
| false |
98 |
1 |
|
T67 |
4 |
|
T68 |
4 |
|
T83 |
3 |
| true |
5627 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T96 |
1 |
|
T53 |
1 |
|
T67 |
8 |
| others[1] |
197 |
1 |
|
T67 |
11 |
|
T68 |
7 |
|
T244 |
1 |
| others[2] |
212 |
1 |
|
T45 |
1 |
|
T67 |
10 |
|
T68 |
6 |
| others[3] |
382 |
1 |
|
T53 |
1 |
|
T35 |
1 |
|
T67 |
22 |
| false |
98 |
1 |
|
T67 |
7 |
|
T68 |
2 |
|
T10 |
1 |
| true |
5655 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T4 |
2 |
|
T22 |
17 |
|
T95 |
13 |
| others[1] |
1207 |
1 |
|
T8 |
1 |
|
T22 |
25 |
|
T95 |
16 |
| others[2] |
1236 |
1 |
|
T22 |
15 |
|
T34 |
1 |
|
T95 |
15 |
| others[3] |
2115 |
1 |
|
T32 |
1 |
|
T22 |
36 |
|
T49 |
1 |
| false |
607 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T22 |
7 |
| true |
360 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
12 |
1 |
|
T77 |
1 |
|
T159 |
1 |
|
T149 |
1 |
| others[1] |
5 |
1 |
|
T386 |
1 |
|
T229 |
1 |
|
T387 |
1 |
| others[2] |
8 |
1 |
|
T155 |
1 |
|
T134 |
1 |
|
T388 |
1 |
| others[3] |
21 |
1 |
|
T50 |
1 |
|
T157 |
1 |
|
T145 |
1 |
| false |
1 |
1 |
|
T389 |
1 |
|
- |
- |
|
- |
- |
| true |
41 |
1 |
|
T7 |
1 |
|
T17 |
1 |
|
T31 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |