Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10759 |
1 |
|
T22 |
100 |
|
T95 |
11 |
|
T57 |
8 |
| others[1] |
796 |
1 |
|
T4 |
1 |
|
T95 |
17 |
|
T57 |
10 |
| others[2] |
775 |
1 |
|
T20 |
1 |
|
T48 |
1 |
|
T81 |
1 |
| others[3] |
1298 |
1 |
|
T4 |
2 |
|
T34 |
1 |
|
T95 |
25 |
| false |
372 |
1 |
|
T95 |
14 |
|
T57 |
2 |
|
T96 |
1 |
| true |
441 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2522 |
1 |
|
T22 |
19 |
|
T95 |
15 |
|
T9 |
1 |
| others[1] |
2427 |
1 |
|
T22 |
25 |
|
T49 |
1 |
|
T95 |
15 |
| others[2] |
2440 |
1 |
|
T4 |
1 |
|
T22 |
12 |
|
T95 |
20 |
| others[3] |
4242 |
1 |
|
T4 |
2 |
|
T22 |
38 |
|
T95 |
22 |
| false |
1298 |
1 |
|
T22 |
6 |
|
T95 |
7 |
|
T57 |
6 |
| true |
1512 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10173 |
1 |
|
T20 |
1 |
|
T22 |
100 |
|
T52 |
191 |
| others[1] |
283 |
1 |
|
T67 |
11 |
|
T68 |
17 |
|
T115 |
1 |
| others[2] |
288 |
1 |
|
T131 |
1 |
|
T67 |
9 |
|
T42 |
1 |
| others[3] |
439 |
1 |
|
T5 |
1 |
|
T49 |
1 |
|
T81 |
1 |
| false |
130 |
1 |
|
T67 |
3 |
|
T94 |
1 |
|
T83 |
6 |
| true |
3128 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10397 |
1 |
|
T32 |
2 |
|
T22 |
100 |
|
T13 |
1 |
| others[1] |
460 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T49 |
1 |
| others[2] |
444 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
1 |
| others[3] |
752 |
1 |
|
T95 |
9 |
|
T57 |
9 |
|
T96 |
1 |
| false |
228 |
1 |
|
T95 |
6 |
|
T77 |
1 |
|
T35 |
1 |
| true |
2160 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10181 |
1 |
|
T22 |
100 |
|
T34 |
1 |
|
T81 |
1 |
| others[1] |
242 |
1 |
|
T67 |
11 |
|
T68 |
13 |
|
T83 |
8 |
| others[2] |
246 |
1 |
|
T53 |
1 |
|
T67 |
7 |
|
T68 |
5 |
| others[3] |
447 |
1 |
|
T60 |
1 |
|
T76 |
1 |
|
T131 |
1 |
| false |
129 |
1 |
|
T82 |
1 |
|
T67 |
2 |
|
T68 |
3 |
| true |
3196 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10179 |
1 |
|
T22 |
100 |
|
T49 |
1 |
|
T52 |
191 |
| others[1] |
245 |
1 |
|
T67 |
10 |
|
T68 |
9 |
|
T117 |
1 |
| others[2] |
256 |
1 |
|
T67 |
6 |
|
T68 |
6 |
|
T116 |
1 |
| others[3] |
407 |
1 |
|
T67 |
13 |
|
T68 |
18 |
|
T105 |
1 |
| false |
125 |
1 |
|
T82 |
1 |
|
T67 |
3 |
|
T68 |
10 |
| true |
3229 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10737 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T32 |
1 |
| others[1] |
776 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T95 |
14 |
| others[2] |
787 |
1 |
|
T4 |
1 |
|
T95 |
15 |
|
T57 |
10 |
| others[3] |
1327 |
1 |
|
T4 |
1 |
|
T95 |
24 |
|
T57 |
11 |
| false |
405 |
1 |
|
T3 |
1 |
|
T95 |
8 |
|
T57 |
3 |
| true |
409 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10709 |
1 |
|
T20 |
1 |
|
T22 |
100 |
|
T49 |
1 |
| others[1] |
752 |
1 |
|
T4 |
1 |
|
T95 |
15 |
|
T57 |
6 |
| others[2] |
813 |
1 |
|
T4 |
2 |
|
T32 |
1 |
|
T95 |
12 |
| others[3] |
1311 |
1 |
|
T95 |
37 |
|
T9 |
1 |
|
T57 |
12 |
| false |
399 |
1 |
|
T95 |
8 |
|
T57 |
5 |
|
T69 |
1 |
| true |
434 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2496 |
1 |
|
T22 |
20 |
|
T95 |
19 |
|
T57 |
7 |
| others[1] |
2505 |
1 |
|
T22 |
16 |
|
T95 |
13 |
|
T57 |
5 |
| others[2] |
2531 |
1 |
|
T4 |
1 |
|
T22 |
17 |
|
T49 |
1 |
| others[3] |
4143 |
1 |
|
T4 |
1 |
|
T22 |
35 |
|
T81 |
1 |
| false |
1297 |
1 |
|
T4 |
1 |
|
T22 |
12 |
|
T95 |
4 |
| true |
1446 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10204 |
1 |
|
T22 |
100 |
|
T33 |
1 |
|
T34 |
1 |
| others[1] |
265 |
1 |
|
T60 |
1 |
|
T45 |
1 |
|
T53 |
1 |
| others[2] |
280 |
1 |
|
T9 |
1 |
|
T67 |
8 |
|
T68 |
8 |
| others[3] |
433 |
1 |
|
T53 |
1 |
|
T67 |
17 |
|
T68 |
21 |
| false |
125 |
1 |
|
T46 |
1 |
|
T97 |
1 |
|
T82 |
1 |
| true |
3111 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10394 |
1 |
|
T3 |
1 |
|
T32 |
1 |
|
T22 |
100 |
| others[1] |
445 |
1 |
|
T32 |
1 |
|
T13 |
1 |
|
T95 |
12 |
| others[2] |
443 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| others[3] |
727 |
1 |
|
T8 |
1 |
|
T23 |
1 |
|
T95 |
9 |
| false |
227 |
1 |
|
T49 |
1 |
|
T95 |
2 |
|
T57 |
2 |
| true |
2182 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10197 |
1 |
|
T22 |
100 |
|
T34 |
1 |
|
T52 |
191 |
| others[1] |
244 |
1 |
|
T67 |
10 |
|
T92 |
1 |
|
T68 |
11 |
| others[2] |
265 |
1 |
|
T96 |
1 |
|
T82 |
1 |
|
T131 |
1 |
| others[3] |
434 |
1 |
|
T9 |
1 |
|
T60 |
1 |
|
T53 |
1 |
| false |
142 |
1 |
|
T33 |
1 |
|
T67 |
5 |
|
T68 |
7 |
| true |
3136 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10199 |
1 |
|
T22 |
100 |
|
T76 |
1 |
|
T52 |
191 |
| others[1] |
227 |
1 |
|
T67 |
9 |
|
T68 |
9 |
|
T83 |
6 |
| others[2] |
276 |
1 |
|
T9 |
1 |
|
T53 |
1 |
|
T67 |
6 |
| others[3] |
419 |
1 |
|
T97 |
1 |
|
T45 |
1 |
|
T67 |
22 |
| false |
134 |
1 |
|
T168 |
1 |
|
T67 |
8 |
|
T68 |
9 |
| true |
3163 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10658 |
1 |
|
T22 |
100 |
|
T49 |
1 |
|
T95 |
20 |
| others[1] |
730 |
1 |
|
T5 |
1 |
|
T23 |
1 |
|
T95 |
11 |
| others[2] |
837 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T95 |
15 |
| others[3] |
1366 |
1 |
|
T95 |
25 |
|
T9 |
1 |
|
T57 |
12 |
| false |
421 |
1 |
|
T4 |
2 |
|
T20 |
1 |
|
T95 |
8 |
| true |
406 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10706 |
1 |
|
T4 |
2 |
|
T22 |
100 |
|
T95 |
22 |
| others[1] |
755 |
1 |
|
T95 |
13 |
|
T57 |
8 |
|
T69 |
3 |
| others[2] |
780 |
1 |
|
T48 |
1 |
|
T95 |
11 |
|
T57 |
6 |
| others[3] |
1338 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T95 |
27 |
| false |
409 |
1 |
|
T13 |
1 |
|
T95 |
6 |
|
T57 |
3 |
| true |
430 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2550 |
1 |
|
T22 |
21 |
|
T49 |
1 |
|
T95 |
18 |
| others[1] |
2488 |
1 |
|
T4 |
1 |
|
T22 |
17 |
|
T95 |
13 |
| others[2] |
2487 |
1 |
|
T4 |
1 |
|
T22 |
14 |
|
T95 |
11 |
| others[3] |
4115 |
1 |
|
T22 |
36 |
|
T95 |
31 |
|
T57 |
12 |
| false |
1348 |
1 |
|
T4 |
1 |
|
T22 |
12 |
|
T95 |
6 |
| true |
1430 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10163 |
1 |
|
T22 |
100 |
|
T33 |
1 |
|
T9 |
1 |
| others[1] |
273 |
1 |
|
T168 |
1 |
|
T67 |
13 |
|
T68 |
12 |
| others[2] |
250 |
1 |
|
T46 |
1 |
|
T97 |
1 |
|
T45 |
1 |
| others[3] |
428 |
1 |
|
T5 |
1 |
|
T49 |
1 |
|
T81 |
1 |
| false |
137 |
1 |
|
T67 |
7 |
|
T68 |
6 |
|
T244 |
1 |
| true |
3167 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10356 |
1 |
|
T4 |
1 |
|
T22 |
100 |
|
T13 |
1 |
| others[1] |
508 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T49 |
1 |
| others[2] |
430 |
1 |
|
T95 |
7 |
|
T57 |
5 |
|
T60 |
1 |
| others[3] |
777 |
1 |
|
T95 |
15 |
|
T9 |
1 |
|
T57 |
3 |
| false |
251 |
1 |
|
T23 |
1 |
|
T34 |
1 |
|
T95 |
2 |
| true |
2096 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10194 |
1 |
|
T22 |
100 |
|
T81 |
1 |
|
T52 |
191 |
| others[1] |
253 |
1 |
|
T49 |
1 |
|
T131 |
1 |
|
T67 |
10 |
| others[2] |
245 |
1 |
|
T34 |
1 |
|
T97 |
1 |
|
T82 |
1 |
| others[3] |
434 |
1 |
|
T33 |
1 |
|
T76 |
1 |
|
T67 |
9 |
| false |
141 |
1 |
|
T67 |
7 |
|
T68 |
5 |
|
T83 |
7 |
| true |
3151 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10145 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T78 |
100 |
| others[1] |
263 |
1 |
|
T81 |
1 |
|
T53 |
2 |
|
T35 |
1 |
| others[2] |
241 |
1 |
|
T9 |
1 |
|
T67 |
9 |
|
T68 |
10 |
| others[3] |
437 |
1 |
|
T97 |
1 |
|
T67 |
13 |
|
T68 |
14 |
| false |
140 |
1 |
|
T67 |
4 |
|
T68 |
7 |
|
T117 |
1 |
| true |
3192 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10684 |
1 |
|
T4 |
1 |
|
T22 |
100 |
|
T23 |
1 |
| others[1] |
750 |
1 |
|
T32 |
1 |
|
T95 |
19 |
|
T57 |
7 |
| others[2] |
853 |
1 |
|
T4 |
1 |
|
T95 |
14 |
|
T57 |
12 |
| others[3] |
1298 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T95 |
25 |
| false |
411 |
1 |
|
T95 |
6 |
|
T57 |
4 |
|
T69 |
4 |
| true |
422 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10709 |
1 |
|
T4 |
1 |
|
T22 |
100 |
|
T95 |
12 |
| others[1] |
752 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T95 |
19 |
| others[2] |
737 |
1 |
|
T95 |
18 |
|
T57 |
10 |
|
T47 |
1 |
| others[3] |
1319 |
1 |
|
T95 |
24 |
|
T57 |
12 |
|
T69 |
4 |
| false |
457 |
1 |
|
T4 |
1 |
|
T95 |
6 |
|
T67 |
10 |
| true |
444 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2456 |
1 |
|
T4 |
1 |
|
T22 |
17 |
|
T49 |
1 |
| others[1] |
2504 |
1 |
|
T22 |
29 |
|
T95 |
12 |
|
T9 |
1 |
| others[2] |
2415 |
1 |
|
T22 |
15 |
|
T95 |
17 |
|
T57 |
11 |
| others[3] |
4271 |
1 |
|
T4 |
2 |
|
T22 |
30 |
|
T95 |
25 |
| false |
1316 |
1 |
|
T22 |
9 |
|
T95 |
15 |
|
T57 |
2 |
| true |
1456 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10208 |
1 |
|
T5 |
1 |
|
T22 |
100 |
|
T9 |
1 |
| others[1] |
260 |
1 |
|
T35 |
1 |
|
T67 |
19 |
|
T68 |
6 |
| others[2] |
275 |
1 |
|
T34 |
1 |
|
T53 |
1 |
|
T67 |
12 |
| others[3] |
443 |
1 |
|
T49 |
1 |
|
T46 |
1 |
|
T47 |
1 |
| false |
153 |
1 |
|
T97 |
1 |
|
T45 |
1 |
|
T67 |
7 |
| true |
3079 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10416 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T22 |
100 |
| others[1] |
433 |
1 |
|
T8 |
1 |
|
T95 |
13 |
|
T57 |
2 |
| others[2] |
457 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T13 |
1 |
| others[3] |
722 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T20 |
1 |
| false |
198 |
1 |
|
T95 |
6 |
|
T57 |
1 |
|
T69 |
1 |
| true |
2192 |
1 |
|
T2 |
1 |
|
T32 |
2 |
|
T48 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10191 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T82 |
1 |
| others[1] |
248 |
1 |
|
T60 |
1 |
|
T35 |
1 |
|
T67 |
7 |
| others[2] |
280 |
1 |
|
T47 |
1 |
|
T67 |
15 |
|
T93 |
1 |
| others[3] |
405 |
1 |
|
T97 |
1 |
|
T168 |
1 |
|
T67 |
15 |
| false |
137 |
1 |
|
T34 |
1 |
|
T45 |
1 |
|
T67 |
8 |
| true |
3157 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10163 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T78 |
100 |
| others[1] |
238 |
1 |
|
T82 |
1 |
|
T67 |
14 |
|
T68 |
12 |
| others[2] |
286 |
1 |
|
T49 |
1 |
|
T168 |
1 |
|
T67 |
14 |
| others[3] |
384 |
1 |
|
T81 |
1 |
|
T96 |
1 |
|
T97 |
1 |
| false |
117 |
1 |
|
T67 |
6 |
|
T68 |
1 |
|
T83 |
6 |
| true |
3230 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10682 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T22 |
100 |
| others[1] |
756 |
1 |
|
T95 |
17 |
|
T9 |
1 |
|
T57 |
5 |
| others[2] |
794 |
1 |
|
T4 |
1 |
|
T95 |
13 |
|
T57 |
8 |
| others[3] |
1336 |
1 |
|
T4 |
1 |
|
T7 |
1 |
|
T49 |
1 |
| false |
439 |
1 |
|
T8 |
1 |
|
T95 |
7 |
|
T57 |
4 |
| true |
411 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10709 |
1 |
|
T4 |
2 |
|
T22 |
100 |
|
T81 |
1 |
| others[1] |
760 |
1 |
|
T95 |
16 |
|
T57 |
10 |
|
T69 |
3 |
| others[2] |
785 |
1 |
|
T95 |
21 |
|
T57 |
4 |
|
T69 |
2 |
| others[3] |
1310 |
1 |
|
T49 |
1 |
|
T95 |
21 |
|
T57 |
7 |
| false |
411 |
1 |
|
T4 |
1 |
|
T95 |
7 |
|
T57 |
4 |
| true |
443 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2555 |
1 |
|
T4 |
2 |
|
T22 |
26 |
|
T95 |
22 |
| others[1] |
2427 |
1 |
|
T22 |
17 |
|
T95 |
10 |
|
T57 |
8 |
| others[2] |
2548 |
1 |
|
T4 |
1 |
|
T22 |
18 |
|
T95 |
14 |
| others[3] |
4093 |
1 |
|
T22 |
26 |
|
T49 |
1 |
|
T95 |
25 |
| false |
1298 |
1 |
|
T22 |
13 |
|
T95 |
8 |
|
T57 |
8 |
| true |
1497 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10169 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T78 |
100 |
| others[1] |
275 |
1 |
|
T96 |
1 |
|
T67 |
13 |
|
T61 |
1 |
| others[2] |
260 |
1 |
|
T67 |
14 |
|
T61 |
2 |
|
T68 |
3 |
| others[3] |
435 |
1 |
|
T33 |
1 |
|
T46 |
1 |
|
T76 |
1 |
| false |
132 |
1 |
|
T67 |
1 |
|
T61 |
1 |
|
T68 |
3 |
| true |
3147 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |