Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10356 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T22 |
100 |
| others[1] |
465 |
1 |
|
T33 |
1 |
|
T95 |
12 |
|
T57 |
4 |
| others[2] |
456 |
1 |
|
T4 |
1 |
|
T49 |
1 |
|
T95 |
4 |
| others[3] |
774 |
1 |
|
T8 |
1 |
|
T23 |
1 |
|
T81 |
1 |
| false |
228 |
1 |
|
T34 |
1 |
|
T95 |
8 |
|
T57 |
3 |
| true |
2139 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10212 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T78 |
100 |
| others[1] |
265 |
1 |
|
T76 |
1 |
|
T67 |
7 |
|
T68 |
7 |
| others[2] |
268 |
1 |
|
T97 |
1 |
|
T131 |
1 |
|
T67 |
6 |
| others[3] |
403 |
1 |
|
T49 |
1 |
|
T9 |
1 |
|
T67 |
23 |
| false |
115 |
1 |
|
T67 |
8 |
|
T68 |
6 |
|
T44 |
1 |
| true |
3155 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10148 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T78 |
100 |
| others[1] |
245 |
1 |
|
T67 |
15 |
|
T42 |
1 |
|
T68 |
13 |
| others[2] |
235 |
1 |
|
T81 |
1 |
|
T96 |
1 |
|
T76 |
1 |
| others[3] |
441 |
1 |
|
T49 |
1 |
|
T82 |
1 |
|
T45 |
1 |
| false |
156 |
1 |
|
T35 |
1 |
|
T67 |
9 |
|
T68 |
4 |
| true |
3193 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10688 |
1 |
|
T4 |
1 |
|
T22 |
100 |
|
T81 |
1 |
| others[1] |
786 |
1 |
|
T7 |
1 |
|
T95 |
16 |
|
T57 |
13 |
| others[2] |
805 |
1 |
|
T4 |
1 |
|
T23 |
1 |
|
T95 |
22 |
| others[3] |
1319 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T95 |
27 |
| false |
395 |
1 |
|
T95 |
5 |
|
T57 |
4 |
|
T69 |
1 |
| true |
425 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10705 |
1 |
|
T4 |
2 |
|
T22 |
100 |
|
T95 |
15 |
| others[1] |
727 |
1 |
|
T3 |
1 |
|
T32 |
1 |
|
T13 |
1 |
| others[2] |
797 |
1 |
|
T95 |
18 |
|
T57 |
12 |
|
T69 |
3 |
| others[3] |
1323 |
1 |
|
T4 |
1 |
|
T95 |
15 |
|
T9 |
1 |
| false |
437 |
1 |
|
T95 |
14 |
|
T57 |
2 |
|
T69 |
1 |
| true |
429 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2434 |
1 |
|
T22 |
14 |
|
T95 |
17 |
|
T57 |
8 |
| others[1] |
2577 |
1 |
|
T22 |
26 |
|
T81 |
1 |
|
T95 |
21 |
| others[2] |
2564 |
1 |
|
T4 |
1 |
|
T22 |
17 |
|
T95 |
12 |
| others[3] |
4072 |
1 |
|
T22 |
33 |
|
T49 |
1 |
|
T95 |
19 |
| false |
1286 |
1 |
|
T4 |
2 |
|
T22 |
10 |
|
T95 |
10 |
| true |
1485 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10222 |
1 |
|
T22 |
100 |
|
T96 |
1 |
|
T52 |
191 |
| others[1] |
270 |
1 |
|
T67 |
7 |
|
T61 |
1 |
|
T68 |
11 |
| others[2] |
259 |
1 |
|
T97 |
1 |
|
T82 |
1 |
|
T67 |
9 |
| others[3] |
459 |
1 |
|
T46 |
1 |
|
T76 |
1 |
|
T47 |
1 |
| false |
130 |
1 |
|
T53 |
1 |
|
T67 |
7 |
|
T68 |
2 |
| true |
3078 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10390 |
1 |
|
T22 |
100 |
|
T81 |
1 |
|
T95 |
7 |
| others[1] |
480 |
1 |
|
T4 |
2 |
|
T13 |
1 |
|
T49 |
1 |
| others[2] |
436 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T95 |
4 |
| others[3] |
713 |
1 |
|
T48 |
1 |
|
T95 |
10 |
|
T57 |
4 |
| false |
226 |
1 |
|
T95 |
5 |
|
T57 |
1 |
|
T60 |
1 |
| true |
2173 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10167 |
1 |
|
T22 |
100 |
|
T33 |
1 |
|
T76 |
1 |
| others[1] |
289 |
1 |
|
T67 |
10 |
|
T68 |
12 |
|
T244 |
1 |
| others[2] |
264 |
1 |
|
T49 |
1 |
|
T34 |
1 |
|
T45 |
1 |
| others[3] |
429 |
1 |
|
T131 |
1 |
|
T53 |
1 |
|
T35 |
1 |
| false |
121 |
1 |
|
T81 |
1 |
|
T67 |
6 |
|
T68 |
2 |
| true |
3148 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10190 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T78 |
100 |
| others[1] |
238 |
1 |
|
T81 |
1 |
|
T53 |
1 |
|
T67 |
17 |
| others[2] |
233 |
1 |
|
T45 |
1 |
|
T67 |
10 |
|
T68 |
11 |
| others[3] |
403 |
1 |
|
T49 |
1 |
|
T67 |
15 |
|
T68 |
17 |
| false |
133 |
1 |
|
T67 |
1 |
|
T68 |
6 |
|
T105 |
1 |
| true |
3221 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10730 |
1 |
|
T22 |
100 |
|
T49 |
1 |
|
T95 |
9 |
| others[1] |
808 |
1 |
|
T4 |
2 |
|
T32 |
1 |
|
T95 |
14 |
| others[2] |
794 |
1 |
|
T95 |
23 |
|
T57 |
12 |
|
T69 |
1 |
| others[3] |
1240 |
1 |
|
T4 |
1 |
|
T23 |
1 |
|
T95 |
22 |
| false |
429 |
1 |
|
T5 |
1 |
|
T48 |
1 |
|
T95 |
11 |
| true |
417 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10717 |
1 |
|
T4 |
1 |
|
T22 |
100 |
|
T95 |
13 |
| others[1] |
778 |
1 |
|
T34 |
1 |
|
T81 |
1 |
|
T95 |
15 |
| others[2] |
719 |
1 |
|
T20 |
1 |
|
T49 |
1 |
|
T95 |
14 |
| others[3] |
1359 |
1 |
|
T4 |
1 |
|
T48 |
1 |
|
T95 |
29 |
| false |
416 |
1 |
|
T4 |
1 |
|
T95 |
8 |
|
T57 |
2 |
| true |
429 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2473 |
1 |
|
T22 |
16 |
|
T49 |
1 |
|
T95 |
20 |
| others[1] |
2545 |
1 |
|
T4 |
2 |
|
T22 |
18 |
|
T95 |
17 |
| others[2] |
2526 |
1 |
|
T22 |
18 |
|
T95 |
12 |
|
T9 |
1 |
| others[3] |
4169 |
1 |
|
T4 |
1 |
|
T22 |
39 |
|
T95 |
21 |
| false |
1280 |
1 |
|
T22 |
9 |
|
T95 |
9 |
|
T57 |
10 |
| true |
1425 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10196 |
1 |
|
T22 |
100 |
|
T34 |
1 |
|
T52 |
191 |
| others[1] |
238 |
1 |
|
T76 |
1 |
|
T168 |
1 |
|
T67 |
4 |
| others[2] |
242 |
1 |
|
T5 |
1 |
|
T67 |
10 |
|
T68 |
10 |
| others[3] |
463 |
1 |
|
T81 |
1 |
|
T53 |
1 |
|
T67 |
17 |
| false |
149 |
1 |
|
T20 |
1 |
|
T97 |
1 |
|
T67 |
3 |
| true |
3130 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10398 |
1 |
|
T22 |
100 |
|
T95 |
7 |
|
T57 |
4 |
| others[1] |
474 |
1 |
|
T4 |
1 |
|
T23 |
1 |
|
T95 |
12 |
| others[2] |
426 |
1 |
|
T3 |
1 |
|
T49 |
1 |
|
T95 |
9 |
| others[3] |
733 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T23 |
1 |
| false |
228 |
1 |
|
T32 |
1 |
|
T95 |
2 |
|
T57 |
2 |
| true |
2159 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10190 |
1 |
|
T22 |
100 |
|
T33 |
1 |
|
T52 |
191 |
| others[1] |
256 |
1 |
|
T67 |
7 |
|
T61 |
4 |
|
T68 |
12 |
| others[2] |
240 |
1 |
|
T53 |
1 |
|
T67 |
7 |
|
T61 |
1 |
| others[3] |
423 |
1 |
|
T131 |
1 |
|
T35 |
1 |
|
T67 |
18 |
| false |
137 |
1 |
|
T81 |
1 |
|
T96 |
1 |
|
T67 |
4 |
| true |
3172 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10157 |
1 |
|
T22 |
100 |
|
T49 |
1 |
|
T97 |
1 |
| others[1] |
249 |
1 |
|
T67 |
8 |
|
T68 |
13 |
|
T10 |
1 |
| others[2] |
242 |
1 |
|
T82 |
1 |
|
T67 |
8 |
|
T68 |
9 |
| others[3] |
395 |
1 |
|
T35 |
1 |
|
T67 |
17 |
|
T68 |
11 |
| false |
138 |
1 |
|
T67 |
6 |
|
T42 |
1 |
|
T68 |
7 |
| true |
3237 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10715 |
1 |
|
T20 |
1 |
|
T7 |
1 |
|
T22 |
100 |
| others[1] |
808 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T95 |
14 |
| others[2] |
779 |
1 |
|
T95 |
13 |
|
T57 |
7 |
|
T69 |
4 |
| others[3] |
1302 |
1 |
|
T32 |
1 |
|
T23 |
1 |
|
T95 |
26 |
| false |
398 |
1 |
|
T95 |
8 |
|
T57 |
3 |
|
T69 |
2 |
| true |
416 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10710 |
1 |
|
T22 |
100 |
|
T34 |
1 |
|
T95 |
19 |
| others[1] |
748 |
1 |
|
T4 |
1 |
|
T95 |
13 |
|
T57 |
3 |
| others[2] |
794 |
1 |
|
T4 |
1 |
|
T49 |
1 |
|
T95 |
15 |
| others[3] |
1335 |
1 |
|
T4 |
1 |
|
T95 |
27 |
|
T57 |
12 |
| false |
393 |
1 |
|
T95 |
5 |
|
T57 |
2 |
|
T96 |
1 |
| true |
438 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2479 |
1 |
|
T4 |
1 |
|
T22 |
17 |
|
T49 |
1 |
| others[1] |
2626 |
1 |
|
T22 |
21 |
|
T95 |
19 |
|
T57 |
7 |
| others[2] |
2474 |
1 |
|
T4 |
2 |
|
T22 |
21 |
|
T95 |
14 |
| others[3] |
4118 |
1 |
|
T22 |
32 |
|
T95 |
25 |
|
T57 |
15 |
| false |
1248 |
1 |
|
T22 |
9 |
|
T95 |
7 |
|
T57 |
4 |
| true |
1473 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10224 |
1 |
|
T5 |
1 |
|
T22 |
100 |
|
T33 |
1 |
| others[1] |
292 |
1 |
|
T96 |
1 |
|
T130 |
1 |
|
T67 |
11 |
| others[2] |
267 |
1 |
|
T34 |
1 |
|
T46 |
1 |
|
T97 |
1 |
| others[3] |
422 |
1 |
|
T60 |
1 |
|
T82 |
1 |
|
T168 |
1 |
| false |
118 |
1 |
|
T67 |
3 |
|
T61 |
1 |
|
T68 |
2 |
| true |
3095 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10364 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T32 |
1 |
| others[1] |
505 |
1 |
|
T5 |
1 |
|
T13 |
1 |
|
T81 |
1 |
| others[2] |
440 |
1 |
|
T32 |
1 |
|
T95 |
9 |
|
T57 |
5 |
| others[3] |
745 |
1 |
|
T20 |
1 |
|
T7 |
1 |
|
T8 |
1 |
| false |
235 |
1 |
|
T95 |
6 |
|
T57 |
1 |
|
T69 |
2 |
| true |
2129 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T48 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10176 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T78 |
100 |
| others[1] |
271 |
1 |
|
T76 |
1 |
|
T97 |
1 |
|
T67 |
14 |
| others[2] |
252 |
1 |
|
T49 |
1 |
|
T60 |
1 |
|
T67 |
14 |
| others[3] |
426 |
1 |
|
T81 |
1 |
|
T9 |
1 |
|
T96 |
1 |
| false |
121 |
1 |
|
T47 |
1 |
|
T67 |
5 |
|
T61 |
1 |
| true |
3172 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10177 |
1 |
|
T22 |
100 |
|
T52 |
191 |
|
T78 |
100 |
| others[1] |
248 |
1 |
|
T96 |
1 |
|
T35 |
1 |
|
T67 |
10 |
| others[2] |
238 |
1 |
|
T76 |
1 |
|
T67 |
8 |
|
T68 |
9 |
| others[3] |
421 |
1 |
|
T97 |
1 |
|
T168 |
1 |
|
T67 |
18 |
| false |
124 |
1 |
|
T67 |
5 |
|
T68 |
5 |
|
T83 |
5 |
| true |
3210 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10712 |
1 |
|
T22 |
100 |
|
T13 |
1 |
|
T95 |
9 |
| others[1] |
787 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T95 |
16 |
| others[2] |
787 |
1 |
|
T4 |
1 |
|
T8 |
1 |
|
T23 |
1 |
| others[3] |
1317 |
1 |
|
T4 |
1 |
|
T32 |
1 |
|
T49 |
1 |
| false |
394 |
1 |
|
T95 |
7 |
|
T57 |
3 |
|
T69 |
1 |
| true |
421 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |