Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	175097	1		T4	2		T5	15		T6	278
auto[FlashEraseBank]	200177	1		T4	1		T5	7		T20	6

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	181436	1		T4	1		T5	19		T6	13
auto[FlashOpProgram]	173468	1		T4	2		T5	3		T6	256
auto[FlashOpErase]	16370	1		T6	9		T22	100		T33	39
auto[FlashOpInvalid]	4000	1		T22	200		T78	200		T308	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	181436	1		T4	1		T5	19		T6	13
op[FlashOpProgram]	173468	1		T4	2		T5	3		T6	256
op[FlashOpErase]	16370	1		T6	9		T22	100		T33	39
read_erase_read	742	1		T6	2		T33	4		T38	2
read_prog_read	982	1		T5	3		T20	1		T49	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	255881	1		T4	3		T5	4		T7	1
auto[FlashPartInfo]	116582	1		T5	17		T6	278		T20	12
auto[FlashPartInfo1]	735	1		T49	3		T9	5		T76	1
auto[FlashPartInfo2]	2076	1		T5	1		T22	6		T33	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	135277	1		T4	1		T5	3		T32	64
auto[FlashPartData]	auto[FlashOpProgram]	112962	1		T4	2		T5	1		T7	1
auto[FlashPartData]	auto[FlashOpErase]	3730	1		T22	97		T33	39		T49	1
auto[FlashPartData]	auto[FlashOpInvalid]	3912	1		T22	194		T78	198		T308	196
auto[FlashPartInfo]	auto[FlashOpRead]	44511	1		T5	15		T6	13		T20	11
auto[FlashPartInfo]	auto[FlashOpProgram]	59395	1		T5	2		T6	256		T20	1
auto[FlashPartInfo]	auto[FlashOpErase]	12602	1		T6	9		T22	2		T38	5
auto[FlashPartInfo]	auto[FlashOpInvalid]	74	1		T22	4		T78	2		T308	2
auto[FlashPartInfo1]	auto[FlashOpRead]	569	1		T49	3		T9	5		T76	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T84	32		T85	32		T86	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T108	1		T390	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T390	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1079	1		T5	1		T22	2		T33	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	949	1		T22	1		T49	1		T9	14
auto[FlashPartInfo2]	auto[FlashOpErase]	36	1		T22	1		T157	1		T98	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T22	2		T308	2		T122	2