Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31636	1		T5	1		T22	400		T52	580
auto[1]	32	1		T60	1		T47	2		T391	2
auto[2]	195	1		T98	4		T221	14		T392	70
auto[3]	150	1		T5	1		T20	1		T46	2

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8013	1		T20	1		T22	100		T46	1
evic_idx[1]	8025	1		T5	2		T22	100		T60	1
evic_idx[2]	7991	1		T22	100		T47	1		T52	145
evic_idx[3]	7984	1		T22	100		T52	145		T78	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31041	1		T22	400		T52	580		T78	400
evic_op[2]	372	1		T5	2		T20	1		T60	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7708	1		T22	100		T52	145		T78	100
evic_idx[0]	evic_op[1]	auto[1]	5	1		T393	5		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	31	1		T392	25		T218	6		-	-
evic_idx[0]	evic_op[1]	auto[3]	28	1		T394	10		T395	18		-	-
evic_idx[0]	evic_op[2]	auto[0]	57	1		T396	3		T129	4		T240	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T391	1		T397	1		T398	1
evic_idx[0]	evic_op[2]	auto[2]	14	1		T221	3		T220	5		T399	6
evic_idx[0]	evic_op[2]	auto[3]	16	1		T20	1		T46	1		T91	1
evic_idx[1]	evic_op[1]	auto[0]	7709	1		T22	100		T52	145		T78	100
evic_idx[1]	evic_op[1]	auto[1]	5	1		T393	3		T394	2		-	-
evic_idx[1]	evic_op[1]	auto[2]	25	1		T392	23		T218	2		-	-
evic_idx[1]	evic_op[1]	auto[3]	32	1		T218	5		T394	8		T395	19
evic_idx[1]	evic_op[2]	auto[0]	62	1		T5	1		T396	3		T129	4
evic_idx[1]	evic_op[2]	auto[1]	5	1		T60	1		T47	1		T391	1
evic_idx[1]	evic_op[2]	auto[2]	24	1		T221	4		T220	14		T399	2
evic_idx[1]	evic_op[2]	auto[3]	13	1		T5	1		T46	1		T131	1
evic_idx[2]	evic_op[1]	auto[0]	7707	1		T22	100		T52	145		T78	100
evic_idx[2]	evic_op[1]	auto[1]	4	1		T393	3		T394	1		-	-
evic_idx[2]	evic_op[1]	auto[2]	20	1		T392	13		T218	7		-	-
evic_idx[2]	evic_op[1]	auto[3]	23	1		T394	9		T395	14		-	-
evic_idx[2]	evic_op[2]	auto[0]	55	1		T396	3		T129	4		T240	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T47	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	21	1		T221	5		T220	9		T399	3
evic_idx[2]	evic_op[2]	auto[3]	10	1		T62	1		T400	1		T213	1
evic_idx[3]	evic_op[1]	auto[0]	7704	1		T22	100		T52	145		T78	100
evic_idx[3]	evic_op[1]	auto[1]	5	1		T393	3		T394	2		-	-
evic_idx[3]	evic_op[1]	auto[2]	15	1		T392	9		T218	6		-	-
evic_idx[3]	evic_op[1]	auto[3]	20	1		T394	7		T395	13		-	-
evic_idx[3]	evic_op[2]	auto[0]	58	1		T204	1		T396	3		T129	4
evic_idx[3]	evic_op[2]	auto[1]	3	1		T397	1		T401	1		T402	1
evic_idx[3]	evic_op[2]	auto[2]	21	1		T221	2		T220	11		T399	7
evic_idx[3]	evic_op[2]	auto[3]	8	1		T62	1		T403	1		T294	1