Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	17367	1		T43	8720		T336	8647		-	-
rd_lvl[2]	20328	1		T43	4960		T336	4649		T337	5497
rd_lvl[3]	9086	1		T235	706		T338	2325		T339	2995
rd_lvl[4]	13620	1		T235	1245		T338	1315		T339	1840
rd_lvl[5]	6005	1		T235	122		T340	1131		T341	1447
rd_lvl[6]	3314	1		T235	782		T341	665		T342	750
rd_lvl[7]	4466	1		T343	1235		T235	631		T344	934
rd_lvl[8]	6996	1		T44	1555		T343	821		T235	630
rd_lvl[9]	2066	1		T44	423		T202	534		T345	228
rd_lvl[10]	3911	1		T202	404		T346	543		T235	3
rd_lvl[11]	4365	1		T42	426		T346	335		T347	447
rd_lvl[12]	4040	1		T42	412		T347	326		T39	816
rd_lvl[13]	3631	1		T348	504		T235	146		T349	454
rd_lvl[14]	2518	1		T348	266		T349	421		T39	12
rd_lvl[15]	1230	1		T40	207		T350	736		T351	287