Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	171727	1		T1	1		T2	1		T3	1
all_pins[1]	171727	1		T1	1		T2	1		T3	1
all_pins[2]	171727	1		T1	1		T2	1		T3	1
all_pins[3]	171727	1		T1	1		T2	1		T3	1
all_pins[4]	171727	1		T1	1		T2	1		T3	1
all_pins[5]	171727	1		T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	865137	1		T1	6		T2	6		T3	6
values[0x1]	165225	1		T35	1224		T42	1676		T43	14944
transitions[0x0=>0x1]	153883	1		T35	1224		T42	1676		T43	13680
transitions[0x1=>0x0]	153867	1		T35	1224		T42	1676		T43	13680

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	171574	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	153	1		T271	5		T272	3		T273	3
all_pins[0]	transitions[0x0=>0x1]	89	1		T271	1		T272	3		T331	4
all_pins[0]	transitions[0x1=>0x0]	65	1		T271	2		T272	1		T273	2
all_pins[1]	values[0x0]	171598	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	129	1		T271	6		T272	1		T273	5
all_pins[1]	transitions[0x0=>0x1]	109	1		T271	5		T272	1		T273	4
all_pins[1]	transitions[0x1=>0x0]	110	1		T40	2		T350	80		T271	2
all_pins[2]	values[0x0]	171597	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	130	1		T40	2		T350	80		T271	3
all_pins[2]	transitions[0x0=>0x1]	33	1		T271	3		T272	1		T273	1
all_pins[2]	transitions[0x1=>0x0]	102991	1		T42	838		T43	13680		T44	1978
all_pins[3]	values[0x0]	68639	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	103088	1		T42	838		T43	13680		T44	1978
all_pins[3]	transitions[0x0=>0x1]	91963	1		T42	838		T43	12416		T44	989
all_pins[3]	transitions[0x1=>0x0]	50552	1		T35	1224		T42	838		T202	938
all_pins[4]	values[0x0]	110050	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	61677	1		T35	1224		T42	838		T43	1264
all_pins[4]	transitions[0x0=>0x1]	61669	1		T35	1224		T42	838		T43	1264
all_pins[4]	transitions[0x1=>0x0]	40	1		T331	2		T330	1		T332	2
all_pins[5]	values[0x0]	171679	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	48	1		T331	3		T330	1		T332	2
all_pins[5]	transitions[0x0=>0x1]	20	1		T332	1		T334	1		T353	1
all_pins[5]	transitions[0x1=>0x0]	109	1		T271	4		T272	2		T273	3