Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	146351	1		T1	2		T2	2		T3	1
all_values[1]	146351	1		T1	2		T2	2		T3	1
all_values[2]	146351	1		T1	2		T2	2		T3	1
all_values[3]	146351	1		T1	2		T2	2		T3	1
all_values[4]	146351	1		T1	2		T2	2		T3	1
all_values[5]	146351	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	298455	1		T1	12		T2	12		T3	6
auto[1]	579651	1		T21	13024		T23	4220		T24	4076

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	431440	1		T1	7		T2	7		T3	4
auto[1]	446666	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	146177	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	174	1		T269	6		T270	1		T336	5
all_values[1]	auto[0]	auto[1]	146210	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	141	1		T269	2		T336	5		T337	5
all_values[2]	auto[0]	auto[0]	1465	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	58	1		T270	1		T336	2		T337	2
all_values[2]	auto[1]	auto[0]	144762	1		T21	3256		T23	1055		T24	1019
all_values[2]	auto[1]	auto[1]	66	1		T269	1		T336	2		T337	2
all_values[3]	auto[0]	auto[0]	1469	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	56	1		T269	3		T270	1		T336	1
all_values[3]	auto[1]	auto[0]	49946	1		T21	814		T23	1055		T24	1019
all_values[3]	auto[1]	auto[1]	94880	1		T21	2442		T31	849		T28	897
all_values[4]	auto[0]	auto[0]	1041	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	463	1		T1	1		T2	1		T5	1
all_values[4]	auto[1]	auto[0]	86563	1		T21	2442		T23	1		T24	1
all_values[4]	auto[1]	auto[1]	58284	1		T21	814		T23	1054		T24	1018
all_values[5]	auto[0]	auto[0]	1423	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	93	1		T32	1		T33	1		T34	1
all_values[5]	auto[1]	auto[0]	144771	1		T21	3256		T23	1055		T24	1019
all_values[5]	auto[1]	auto[1]	64	1		T270	1		T336	1		T337	2