Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T6 |
14 |
|
T17 |
1 |
|
T36 |
1 |
| others[1] |
218 |
1 |
|
T6 |
14 |
|
T27 |
11 |
|
T60 |
7 |
| others[2] |
203 |
1 |
|
T6 |
11 |
|
T27 |
8 |
|
T60 |
7 |
| others[3] |
374 |
1 |
|
T6 |
18 |
|
T27 |
18 |
|
T60 |
24 |
| false |
89 |
1 |
|
T6 |
3 |
|
T27 |
2 |
|
T60 |
7 |
| true |
11986 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
211 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7523 |
1 |
|
T4 |
211 |
|
T6 |
18 |
|
T42 |
52 |
| others[1] |
1232 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
20 |
| others[2] |
1225 |
1 |
|
T6 |
11 |
|
T15 |
1 |
|
T36 |
1 |
| others[3] |
2136 |
1 |
|
T2 |
1 |
|
T6 |
41 |
|
T56 |
1 |
| false |
633 |
1 |
|
T6 |
11 |
|
T91 |
1 |
|
T27 |
10 |
| true |
351 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7497 |
1 |
|
T4 |
211 |
|
T6 |
19 |
|
T42 |
52 |
| others[1] |
1269 |
1 |
|
T2 |
1 |
|
T6 |
25 |
|
T18 |
1 |
| others[2] |
1282 |
1 |
|
T6 |
24 |
|
T53 |
1 |
|
T27 |
16 |
| others[3] |
2085 |
1 |
|
T5 |
1 |
|
T6 |
26 |
|
T15 |
1 |
| false |
634 |
1 |
|
T1 |
1 |
|
T6 |
7 |
|
T91 |
1 |
| true |
333 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T6 |
4 |
|
T27 |
7 |
|
T60 |
4 |
| others[1] |
108 |
1 |
|
T6 |
2 |
|
T27 |
2 |
|
T60 |
3 |
| others[2] |
110 |
1 |
|
T6 |
5 |
|
T17 |
1 |
|
T56 |
1 |
| others[3] |
175 |
1 |
|
T6 |
11 |
|
T56 |
1 |
|
T27 |
5 |
| false |
55 |
1 |
|
T27 |
2 |
|
T60 |
2 |
|
T79 |
2 |
| true |
12546 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
211 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T6 |
10 |
|
T32 |
1 |
|
T27 |
9 |
| others[1] |
213 |
1 |
|
T14 |
1 |
|
T6 |
14 |
|
T27 |
7 |
| others[2] |
249 |
1 |
|
T6 |
11 |
|
T27 |
7 |
|
T60 |
11 |
| others[3] |
391 |
1 |
|
T6 |
11 |
|
T27 |
21 |
|
T60 |
18 |
| false |
133 |
1 |
|
T6 |
7 |
|
T56 |
1 |
|
T27 |
7 |
| true |
11878 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
211 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7299 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
211 |
| others[1] |
1092 |
1 |
|
T6 |
12 |
|
T15 |
1 |
|
T91 |
1 |
| others[2] |
1074 |
1 |
|
T6 |
22 |
|
T56 |
1 |
|
T71 |
1 |
| others[3] |
1802 |
1 |
|
T5 |
1 |
|
T6 |
34 |
|
T17 |
1 |
| false |
533 |
1 |
|
T6 |
9 |
|
T16 |
1 |
|
T27 |
10 |
| true |
1300 |
1 |
|
T38 |
1 |
|
T32 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T6 |
16 |
|
T36 |
1 |
|
T27 |
9 |
| others[1] |
225 |
1 |
|
T6 |
10 |
|
T27 |
10 |
|
T60 |
6 |
| others[2] |
226 |
1 |
|
T6 |
13 |
|
T17 |
1 |
|
T56 |
1 |
| others[3] |
383 |
1 |
|
T6 |
17 |
|
T38 |
1 |
|
T32 |
1 |
| false |
129 |
1 |
|
T6 |
2 |
|
T27 |
5 |
|
T60 |
5 |
| true |
11905 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
211 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T6 |
17 |
|
T36 |
1 |
|
T27 |
9 |
| others[1] |
225 |
1 |
|
T6 |
8 |
|
T16 |
1 |
|
T27 |
10 |
| others[2] |
215 |
1 |
|
T6 |
7 |
|
T27 |
4 |
|
T60 |
7 |
| others[3] |
358 |
1 |
|
T6 |
20 |
|
T17 |
1 |
|
T27 |
23 |
| false |
120 |
1 |
|
T6 |
5 |
|
T27 |
4 |
|
T60 |
7 |
| true |
11973 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
211 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7436 |
1 |
|
T4 |
211 |
|
T6 |
20 |
|
T18 |
1 |
| others[1] |
1271 |
1 |
|
T6 |
17 |
|
T27 |
18 |
|
T60 |
19 |
| others[2] |
1294 |
1 |
|
T2 |
1 |
|
T6 |
22 |
|
T56 |
1 |
| others[3] |
2075 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
34 |
| false |
668 |
1 |
|
T6 |
8 |
|
T53 |
1 |
|
T27 |
9 |
| true |
356 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T1 |
1 |
|
T6 |
21 |
|
T91 |
1 |
| others[1] |
1275 |
1 |
|
T6 |
23 |
|
T27 |
21 |
|
T21 |
1 |
| others[2] |
1340 |
1 |
|
T2 |
1 |
|
T6 |
18 |
|
T15 |
1 |
| others[3] |
2039 |
1 |
|
T5 |
1 |
|
T6 |
28 |
|
T18 |
1 |
| false |
665 |
1 |
|
T6 |
11 |
|
T27 |
8 |
|
T60 |
7 |
| true |
336 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
70 |
1 |
|
T6 |
4 |
|
T27 |
2 |
|
T60 |
1 |
| others[1] |
112 |
1 |
|
T6 |
3 |
|
T56 |
1 |
|
T36 |
1 |
| others[2] |
93 |
1 |
|
T6 |
5 |
|
T27 |
2 |
|
T60 |
2 |
| others[3] |
170 |
1 |
|
T6 |
6 |
|
T56 |
1 |
|
T27 |
11 |
| false |
57 |
1 |
|
T6 |
4 |
|
T27 |
2 |
|
T79 |
1 |
| true |
6412 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T14 |
1 |
|
T6 |
6 |
|
T56 |
1 |
| others[1] |
226 |
1 |
|
T6 |
11 |
|
T16 |
1 |
|
T27 |
12 |
| others[2] |
222 |
1 |
|
T6 |
6 |
|
T20 |
1 |
|
T27 |
10 |
| others[3] |
367 |
1 |
|
T6 |
13 |
|
T17 |
1 |
|
T32 |
1 |
| false |
124 |
1 |
|
T6 |
6 |
|
T27 |
8 |
|
T60 |
6 |
| true |
5774 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T6 |
22 |
|
T15 |
1 |
|
T20 |
1 |
| others[1] |
1057 |
1 |
|
T5 |
1 |
|
T6 |
17 |
|
T38 |
1 |
| others[2] |
1104 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T6 |
23 |
| others[3] |
1771 |
1 |
|
T1 |
1 |
|
T6 |
32 |
|
T91 |
1 |
| false |
549 |
1 |
|
T6 |
7 |
|
T56 |
1 |
|
T27 |
11 |
| true |
1338 |
1 |
|
T16 |
1 |
|
T52 |
1 |
|
T86 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T6 |
4 |
|
T56 |
1 |
|
T27 |
9 |
| others[1] |
220 |
1 |
|
T6 |
11 |
|
T27 |
11 |
|
T86 |
1 |
| others[2] |
207 |
1 |
|
T6 |
10 |
|
T27 |
6 |
|
T60 |
8 |
| others[3] |
362 |
1 |
|
T6 |
21 |
|
T20 |
1 |
|
T56 |
1 |
| false |
110 |
1 |
|
T6 |
5 |
|
T32 |
1 |
|
T27 |
4 |
| true |
5783 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T6 |
9 |
|
T16 |
1 |
|
T17 |
1 |
| others[1] |
207 |
1 |
|
T6 |
11 |
|
T56 |
1 |
|
T27 |
2 |
| others[2] |
235 |
1 |
|
T6 |
15 |
|
T27 |
7 |
|
T60 |
10 |
| others[3] |
352 |
1 |
|
T6 |
20 |
|
T27 |
16 |
|
T60 |
13 |
| false |
110 |
1 |
|
T6 |
5 |
|
T27 |
6 |
|
T60 |
6 |
| true |
5796 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T6 |
29 |
|
T15 |
1 |
|
T56 |
1 |
| others[1] |
1305 |
1 |
|
T6 |
17 |
|
T91 |
1 |
|
T27 |
19 |
| others[2] |
1280 |
1 |
|
T5 |
1 |
|
T6 |
14 |
|
T18 |
1 |
| others[3] |
2056 |
1 |
|
T1 |
1 |
|
T6 |
27 |
|
T56 |
1 |
| false |
671 |
1 |
|
T2 |
1 |
|
T6 |
14 |
|
T27 |
14 |
| true |
363 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
22 |
| others[1] |
1252 |
1 |
|
T6 |
14 |
|
T91 |
1 |
|
T27 |
21 |
| others[2] |
1269 |
1 |
|
T5 |
1 |
|
T6 |
21 |
|
T18 |
1 |
| others[3] |
2122 |
1 |
|
T6 |
32 |
|
T15 |
1 |
|
T53 |
1 |
| false |
669 |
1 |
|
T6 |
12 |
|
T56 |
1 |
|
T27 |
9 |
| true |
341 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T6 |
6 |
|
T27 |
6 |
|
T60 |
2 |
| others[1] |
98 |
1 |
|
T6 |
4 |
|
T56 |
1 |
|
T27 |
5 |
| others[2] |
117 |
1 |
|
T6 |
5 |
|
T36 |
1 |
|
T27 |
3 |
| others[3] |
183 |
1 |
|
T6 |
6 |
|
T16 |
1 |
|
T27 |
7 |
| false |
60 |
1 |
|
T6 |
3 |
|
T56 |
1 |
|
T79 |
2 |
| true |
6356 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T6 |
7 |
|
T27 |
12 |
|
T60 |
8 |
| others[1] |
231 |
1 |
|
T6 |
15 |
|
T27 |
11 |
|
T86 |
1 |
| others[2] |
200 |
1 |
|
T6 |
9 |
|
T27 |
8 |
|
T60 |
10 |
| others[3] |
374 |
1 |
|
T6 |
18 |
|
T38 |
1 |
|
T27 |
17 |
| false |
124 |
1 |
|
T6 |
5 |
|
T27 |
8 |
|
T60 |
9 |
| true |
5752 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1082 |
1 |
|
T5 |
1 |
|
T6 |
19 |
|
T56 |
1 |
| others[1] |
996 |
1 |
|
T2 |
1 |
|
T6 |
15 |
|
T18 |
1 |
| others[2] |
1082 |
1 |
|
T1 |
1 |
|
T6 |
16 |
|
T15 |
1 |
| others[3] |
1794 |
1 |
|
T6 |
40 |
|
T16 |
1 |
|
T38 |
1 |
| false |
571 |
1 |
|
T14 |
1 |
|
T6 |
11 |
|
T17 |
1 |
| true |
1389 |
1 |
|
T32 |
1 |
|
T20 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T6 |
7 |
|
T27 |
10 |
|
T60 |
9 |
| others[1] |
241 |
1 |
|
T6 |
8 |
|
T27 |
14 |
|
T60 |
11 |
| others[2] |
213 |
1 |
|
T6 |
10 |
|
T27 |
8 |
|
T86 |
1 |
| others[3] |
397 |
1 |
|
T6 |
20 |
|
T17 |
1 |
|
T38 |
1 |
| false |
124 |
1 |
|
T6 |
7 |
|
T27 |
4 |
|
T60 |
4 |
| true |
5723 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T6 |
6 |
|
T27 |
11 |
|
T60 |
14 |
| others[1] |
218 |
1 |
|
T6 |
8 |
|
T16 |
1 |
|
T27 |
11 |
| others[2] |
245 |
1 |
|
T6 |
11 |
|
T27 |
11 |
|
T60 |
8 |
| others[3] |
341 |
1 |
|
T6 |
15 |
|
T17 |
1 |
|
T32 |
1 |
| false |
137 |
1 |
|
T6 |
9 |
|
T38 |
1 |
|
T27 |
6 |
| true |
5746 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1205 |
1 |
|
T6 |
23 |
|
T27 |
25 |
|
T60 |
17 |
| others[1] |
1271 |
1 |
|
T6 |
22 |
|
T38 |
1 |
|
T36 |
1 |
| others[2] |
1202 |
1 |
|
T1 |
1 |
|
T6 |
15 |
|
T15 |
1 |
| others[3] |
2137 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
31 |
| false |
740 |
1 |
|
T6 |
10 |
|
T91 |
1 |
|
T27 |
9 |
| true |
359 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T1 |
1 |
|
T6 |
26 |
|
T27 |
18 |
| others[1] |
1301 |
1 |
|
T2 |
1 |
|
T6 |
21 |
|
T15 |
1 |
| others[2] |
1253 |
1 |
|
T6 |
19 |
|
T18 |
1 |
|
T91 |
1 |
| others[3] |
2140 |
1 |
|
T5 |
1 |
|
T6 |
28 |
|
T53 |
1 |
| false |
636 |
1 |
|
T6 |
7 |
|
T56 |
1 |
|
T27 |
11 |
| true |
321 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T6 |
2 |
|
T27 |
5 |
|
T60 |
5 |
| others[1] |
93 |
1 |
|
T6 |
2 |
|
T27 |
1 |
|
T60 |
4 |
| others[2] |
102 |
1 |
|
T6 |
4 |
|
T27 |
5 |
|
T60 |
5 |
| others[3] |
149 |
1 |
|
T6 |
4 |
|
T56 |
1 |
|
T36 |
1 |
| false |
60 |
1 |
|
T6 |
2 |
|
T56 |
1 |
|
T27 |
4 |
| true |
6403 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T6 |
3 |
|
T27 |
10 |
|
T60 |
8 |
| others[1] |
235 |
1 |
|
T6 |
13 |
|
T17 |
1 |
|
T27 |
4 |
| others[2] |
205 |
1 |
|
T6 |
3 |
|
T27 |
12 |
|
T86 |
1 |
| others[3] |
397 |
1 |
|
T14 |
1 |
|
T6 |
21 |
|
T32 |
1 |
| false |
117 |
1 |
|
T6 |
6 |
|
T27 |
3 |
|
T60 |
5 |
| true |
5748 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1086 |
1 |
|
T6 |
21 |
|
T18 |
1 |
|
T53 |
1 |
| others[1] |
1086 |
1 |
|
T14 |
1 |
|
T6 |
21 |
|
T15 |
1 |
| others[2] |
1050 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
13 |
| others[3] |
1806 |
1 |
|
T2 |
1 |
|
T6 |
37 |
|
T10 |
1 |
| false |
539 |
1 |
|
T6 |
9 |
|
T27 |
7 |
|
T60 |
4 |
| true |
1347 |
1 |
|
T38 |
1 |
|
T71 |
1 |
|
T90 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T6 |
10 |
|
T27 |
7 |
|
T86 |
1 |
| others[1] |
220 |
1 |
|
T6 |
10 |
|
T27 |
8 |
|
T60 |
15 |
| others[2] |
238 |
1 |
|
T6 |
7 |
|
T56 |
1 |
|
T27 |
12 |
| others[3] |
369 |
1 |
|
T6 |
21 |
|
T56 |
1 |
|
T27 |
16 |
| false |
114 |
1 |
|
T6 |
8 |
|
T38 |
1 |
|
T27 |
8 |
| true |
5758 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T6 |
6 |
|
T27 |
5 |
|
T86 |
1 |
| others[1] |
210 |
1 |
|
T6 |
13 |
|
T27 |
8 |
|
T60 |
7 |
| others[2] |
228 |
1 |
|
T6 |
12 |
|
T56 |
1 |
|
T27 |
16 |
| others[3] |
354 |
1 |
|
T6 |
12 |
|
T17 |
1 |
|
T32 |
1 |
| false |
96 |
1 |
|
T6 |
3 |
|
T27 |
6 |
|
T60 |
4 |
| true |
5810 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T2 |
1 |
|
T6 |
16 |
|
T36 |
1 |
| others[1] |
1321 |
1 |
|
T6 |
20 |
|
T18 |
1 |
|
T32 |
1 |
| others[2] |
1296 |
1 |
|
T6 |
23 |
|
T15 |
1 |
|
T56 |
1 |
| others[3] |
2040 |
1 |
|
T5 |
1 |
|
T6 |
33 |
|
T91 |
1 |
| false |
675 |
1 |
|
T1 |
1 |
|
T6 |
9 |
|
T27 |
11 |
| true |
349 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T5 |
1 |
|
T6 |
25 |
|
T56 |
1 |
| others[1] |
1329 |
1 |
|
T6 |
22 |
|
T56 |
1 |
|
T27 |
25 |
| others[2] |
1284 |
1 |
|
T1 |
1 |
|
T6 |
20 |
|
T15 |
1 |
| others[3] |
2121 |
1 |
|
T2 |
1 |
|
T6 |
26 |
|
T53 |
1 |
| false |
612 |
1 |
|
T6 |
8 |
|
T27 |
12 |
|
T21 |
1 |
| true |
339 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |