Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T6 |
8 |
|
T56 |
1 |
|
T27 |
3 |
| others[1] |
127 |
1 |
|
T6 |
2 |
|
T27 |
9 |
|
T60 |
2 |
| others[2] |
114 |
1 |
|
T6 |
3 |
|
T27 |
4 |
|
T60 |
4 |
| others[3] |
184 |
1 |
|
T6 |
6 |
|
T56 |
1 |
|
T36 |
1 |
| false |
34 |
1 |
|
T27 |
1 |
|
T60 |
1 |
|
T79 |
2 |
| true |
6343 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T6 |
7 |
|
T56 |
1 |
|
T27 |
1 |
| others[1] |
252 |
1 |
|
T6 |
4 |
|
T56 |
1 |
|
T27 |
13 |
| others[2] |
208 |
1 |
|
T6 |
10 |
|
T16 |
1 |
|
T27 |
10 |
| others[3] |
343 |
1 |
|
T6 |
17 |
|
T32 |
1 |
|
T27 |
14 |
| false |
125 |
1 |
|
T6 |
2 |
|
T27 |
6 |
|
T60 |
2 |
| true |
5767 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1097 |
1 |
|
T6 |
21 |
|
T53 |
1 |
|
T27 |
17 |
| others[1] |
1093 |
1 |
|
T6 |
19 |
|
T17 |
1 |
|
T32 |
1 |
| others[2] |
1076 |
1 |
|
T1 |
1 |
|
T6 |
14 |
|
T15 |
1 |
| others[3] |
1786 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T5 |
1 |
| false |
537 |
1 |
|
T6 |
13 |
|
T27 |
15 |
|
T60 |
11 |
| true |
1325 |
1 |
|
T16 |
1 |
|
T10 |
1 |
|
T52 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
260 |
1 |
|
T6 |
12 |
|
T38 |
1 |
|
T56 |
1 |
| others[1] |
238 |
1 |
|
T6 |
8 |
|
T16 |
1 |
|
T27 |
13 |
| others[2] |
203 |
1 |
|
T6 |
10 |
|
T27 |
13 |
|
T60 |
7 |
| others[3] |
359 |
1 |
|
T6 |
12 |
|
T17 |
1 |
|
T32 |
1 |
| false |
107 |
1 |
|
T6 |
3 |
|
T27 |
3 |
|
T60 |
5 |
| true |
5747 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T6 |
5 |
|
T27 |
4 |
|
T60 |
8 |
| others[1] |
209 |
1 |
|
T6 |
11 |
|
T36 |
1 |
|
T27 |
16 |
| others[2] |
227 |
1 |
|
T6 |
10 |
|
T32 |
1 |
|
T27 |
10 |
| others[3] |
375 |
1 |
|
T6 |
15 |
|
T38 |
1 |
|
T56 |
2 |
| false |
130 |
1 |
|
T6 |
10 |
|
T27 |
6 |
|
T60 |
9 |
| true |
5767 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T6 |
15 |
|
T71 |
1 |
|
T27 |
24 |
| others[1] |
1231 |
1 |
|
T6 |
15 |
|
T91 |
1 |
|
T27 |
21 |
| others[2] |
1261 |
1 |
|
T2 |
1 |
|
T6 |
18 |
|
T54 |
1 |
| others[3] |
2147 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
40 |
| false |
676 |
1 |
|
T6 |
13 |
|
T53 |
1 |
|
T27 |
8 |
| true |
354 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1308 |
1 |
|
T1 |
1 |
|
T6 |
22 |
|
T15 |
1 |
| others[1] |
1255 |
1 |
|
T5 |
1 |
|
T6 |
21 |
|
T56 |
1 |
| others[2] |
1270 |
1 |
|
T2 |
1 |
|
T6 |
18 |
|
T18 |
1 |
| others[3] |
2073 |
1 |
|
T6 |
32 |
|
T91 |
1 |
|
T27 |
31 |
| false |
672 |
1 |
|
T6 |
8 |
|
T36 |
1 |
|
T27 |
13 |
| true |
336 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T6 |
5 |
|
T36 |
1 |
|
T27 |
2 |
| others[1] |
108 |
1 |
|
T6 |
4 |
|
T60 |
6 |
|
T79 |
4 |
| others[2] |
99 |
1 |
|
T6 |
4 |
|
T27 |
5 |
|
T60 |
1 |
| others[3] |
194 |
1 |
|
T6 |
2 |
|
T56 |
2 |
|
T27 |
8 |
| false |
53 |
1 |
|
T27 |
2 |
|
T95 |
3 |
|
T377 |
1 |
| true |
6357 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T6 |
6 |
|
T17 |
1 |
|
T38 |
1 |
| others[1] |
215 |
1 |
|
T14 |
1 |
|
T6 |
11 |
|
T16 |
1 |
| others[2] |
240 |
1 |
|
T6 |
10 |
|
T20 |
1 |
|
T27 |
13 |
| others[3] |
384 |
1 |
|
T6 |
18 |
|
T36 |
1 |
|
T27 |
20 |
| false |
109 |
1 |
|
T6 |
5 |
|
T56 |
1 |
|
T27 |
1 |
| true |
5741 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T2 |
1 |
|
T6 |
21 |
|
T56 |
1 |
| others[1] |
1099 |
1 |
|
T6 |
17 |
|
T38 |
1 |
|
T56 |
1 |
| others[2] |
1094 |
1 |
|
T6 |
19 |
|
T18 |
1 |
|
T91 |
1 |
| others[3] |
1751 |
1 |
|
T5 |
1 |
|
T6 |
31 |
|
T15 |
1 |
| false |
559 |
1 |
|
T1 |
1 |
|
T6 |
13 |
|
T20 |
1 |
| true |
1345 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T6 |
10 |
|
T38 |
1 |
|
T27 |
10 |
| others[1] |
244 |
1 |
|
T6 |
6 |
|
T27 |
10 |
|
T60 |
8 |
| others[2] |
207 |
1 |
|
T6 |
5 |
|
T27 |
9 |
|
T60 |
3 |
| others[3] |
357 |
1 |
|
T6 |
23 |
|
T20 |
1 |
|
T56 |
1 |
| false |
127 |
1 |
|
T6 |
4 |
|
T27 |
6 |
|
T60 |
9 |
| true |
5757 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T6 |
15 |
|
T27 |
6 |
|
T60 |
13 |
| others[1] |
205 |
1 |
|
T6 |
14 |
|
T17 |
1 |
|
T27 |
12 |
| others[2] |
221 |
1 |
|
T6 |
11 |
|
T36 |
1 |
|
T27 |
15 |
| others[3] |
363 |
1 |
|
T6 |
13 |
|
T32 |
1 |
|
T56 |
1 |
| false |
117 |
1 |
|
T6 |
2 |
|
T27 |
6 |
|
T60 |
5 |
| true |
5789 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T6 |
21 |
|
T18 |
1 |
|
T36 |
1 |
| others[1] |
1241 |
1 |
|
T6 |
19 |
|
T27 |
23 |
|
T60 |
16 |
| others[2] |
1292 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
17 |
| others[3] |
2092 |
1 |
|
T6 |
37 |
|
T15 |
1 |
|
T91 |
1 |
| false |
676 |
1 |
|
T2 |
1 |
|
T6 |
7 |
|
T27 |
6 |
| true |
354 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1300 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
19 |
| others[1] |
1231 |
1 |
|
T5 |
1 |
|
T6 |
14 |
|
T53 |
1 |
| others[2] |
1243 |
1 |
|
T6 |
21 |
|
T91 |
1 |
|
T56 |
1 |
| others[3] |
2168 |
1 |
|
T6 |
41 |
|
T15 |
1 |
|
T27 |
28 |
| false |
641 |
1 |
|
T6 |
6 |
|
T18 |
1 |
|
T27 |
9 |
| true |
331 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T6 |
4 |
|
T36 |
1 |
|
T27 |
2 |
| others[1] |
90 |
1 |
|
T6 |
2 |
|
T56 |
1 |
|
T27 |
5 |
| others[2] |
92 |
1 |
|
T6 |
5 |
|
T27 |
2 |
|
T60 |
2 |
| others[3] |
165 |
1 |
|
T6 |
4 |
|
T17 |
1 |
|
T27 |
9 |
| false |
56 |
1 |
|
T6 |
1 |
|
T56 |
1 |
|
T27 |
2 |
| true |
6417 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T6 |
9 |
|
T17 |
1 |
|
T27 |
14 |
| others[1] |
241 |
1 |
|
T6 |
12 |
|
T27 |
10 |
|
T60 |
2 |
| others[2] |
248 |
1 |
|
T14 |
1 |
|
T6 |
8 |
|
T56 |
1 |
| others[3] |
366 |
1 |
|
T6 |
12 |
|
T27 |
17 |
|
T60 |
17 |
| false |
102 |
1 |
|
T6 |
1 |
|
T38 |
1 |
|
T60 |
7 |
| true |
5745 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1118 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T6 |
25 |
| others[1] |
1106 |
1 |
|
T6 |
21 |
|
T91 |
1 |
|
T56 |
1 |
| others[2] |
1060 |
1 |
|
T6 |
22 |
|
T15 |
1 |
|
T18 |
1 |
| others[3] |
1748 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
26 |
| false |
559 |
1 |
|
T6 |
7 |
|
T38 |
1 |
|
T53 |
1 |
| true |
1323 |
1 |
|
T16 |
1 |
|
T20 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T6 |
16 |
|
T27 |
7 |
|
T60 |
8 |
| others[1] |
207 |
1 |
|
T6 |
6 |
|
T56 |
1 |
|
T27 |
12 |
| others[2] |
218 |
1 |
|
T6 |
8 |
|
T17 |
1 |
|
T32 |
1 |
| others[3] |
342 |
1 |
|
T6 |
13 |
|
T27 |
13 |
|
T86 |
1 |
| false |
150 |
1 |
|
T6 |
4 |
|
T27 |
9 |
|
T60 |
9 |
| true |
5752 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T6 |
11 |
|
T27 |
8 |
|
T60 |
7 |
| others[1] |
204 |
1 |
|
T6 |
8 |
|
T27 |
10 |
|
T60 |
11 |
| others[2] |
202 |
1 |
|
T6 |
7 |
|
T38 |
1 |
|
T27 |
10 |
| others[3] |
371 |
1 |
|
T6 |
14 |
|
T16 |
1 |
|
T27 |
16 |
| false |
101 |
1 |
|
T6 |
6 |
|
T32 |
1 |
|
T27 |
4 |
| true |
5824 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1349 |
1 |
|
T5 |
1 |
|
T6 |
19 |
|
T53 |
1 |
| others[1] |
1280 |
1 |
|
T2 |
1 |
|
T6 |
18 |
|
T56 |
1 |
| others[2] |
1177 |
1 |
|
T1 |
1 |
|
T6 |
16 |
|
T15 |
1 |
| others[3] |
2132 |
1 |
|
T6 |
36 |
|
T56 |
1 |
|
T54 |
1 |
| false |
628 |
1 |
|
T6 |
12 |
|
T18 |
1 |
|
T27 |
10 |
| true |
348 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T5 |
1 |
|
T6 |
15 |
|
T56 |
1 |
| others[1] |
1272 |
1 |
|
T1 |
1 |
|
T6 |
20 |
|
T18 |
1 |
| others[2] |
1224 |
1 |
|
T6 |
28 |
|
T27 |
18 |
|
T60 |
23 |
| others[3] |
2144 |
1 |
|
T2 |
1 |
|
T6 |
31 |
|
T15 |
1 |
| false |
656 |
1 |
|
T6 |
7 |
|
T56 |
1 |
|
T27 |
16 |
| true |
337 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
94 |
1 |
|
T6 |
1 |
|
T27 |
3 |
|
T60 |
2 |
| others[1] |
81 |
1 |
|
T6 |
5 |
|
T56 |
1 |
|
T27 |
2 |
| others[2] |
119 |
1 |
|
T6 |
4 |
|
T36 |
1 |
|
T27 |
5 |
| others[3] |
173 |
1 |
|
T6 |
6 |
|
T56 |
1 |
|
T27 |
5 |
| false |
56 |
1 |
|
T6 |
1 |
|
T60 |
1 |
|
T79 |
2 |
| true |
6391 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T6 |
12 |
|
T17 |
1 |
|
T27 |
11 |
| others[1] |
217 |
1 |
|
T6 |
8 |
|
T27 |
10 |
|
T60 |
13 |
| others[2] |
237 |
1 |
|
T6 |
10 |
|
T27 |
8 |
|
T60 |
13 |
| others[3] |
360 |
1 |
|
T6 |
17 |
|
T27 |
17 |
|
T60 |
13 |
| false |
124 |
1 |
|
T14 |
1 |
|
T6 |
4 |
|
T27 |
5 |
| true |
5744 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T6 |
19 |
|
T27 |
19 |
|
T55 |
1 |
| others[1] |
1111 |
1 |
|
T1 |
1 |
|
T6 |
21 |
|
T38 |
1 |
| others[2] |
1058 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
25 |
| others[3] |
1808 |
1 |
|
T14 |
1 |
|
T6 |
28 |
|
T15 |
1 |
| false |
563 |
1 |
|
T6 |
8 |
|
T32 |
1 |
|
T20 |
1 |
| true |
1296 |
1 |
|
T16 |
1 |
|
T52 |
1 |
|
T86 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T6 |
8 |
|
T27 |
8 |
|
T60 |
13 |
| others[1] |
219 |
1 |
|
T6 |
12 |
|
T27 |
7 |
|
T60 |
12 |
| others[2] |
215 |
1 |
|
T6 |
7 |
|
T32 |
1 |
|
T27 |
10 |
| others[3] |
366 |
1 |
|
T6 |
15 |
|
T38 |
1 |
|
T27 |
15 |
| false |
110 |
1 |
|
T6 |
7 |
|
T27 |
3 |
|
T60 |
3 |
| true |
5775 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T6 |
8 |
|
T27 |
7 |
|
T60 |
12 |
| others[1] |
243 |
1 |
|
T6 |
15 |
|
T32 |
1 |
|
T36 |
1 |
| others[2] |
215 |
1 |
|
T6 |
9 |
|
T56 |
1 |
|
T27 |
11 |
| others[3] |
369 |
1 |
|
T6 |
18 |
|
T27 |
18 |
|
T60 |
15 |
| false |
113 |
1 |
|
T6 |
1 |
|
T27 |
8 |
|
T60 |
8 |
| true |
5776 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T6 |
17 |
|
T15 |
1 |
|
T27 |
12 |
| others[1] |
1262 |
1 |
|
T6 |
20 |
|
T27 |
20 |
|
T60 |
19 |
| others[2] |
1289 |
1 |
|
T6 |
15 |
|
T18 |
1 |
|
T91 |
1 |
| others[3] |
2140 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
44 |
| false |
654 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T53 |
1 |
| true |
350 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T6 |
20 |
|
T56 |
1 |
|
T53 |
1 |
| others[1] |
1279 |
1 |
|
T2 |
1 |
|
T6 |
19 |
|
T27 |
14 |
| others[2] |
1275 |
1 |
|
T6 |
22 |
|
T36 |
1 |
|
T27 |
20 |
| others[3] |
2167 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
33 |
| false |
625 |
1 |
|
T6 |
7 |
|
T91 |
1 |
|
T27 |
7 |
| true |
334 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
121 |
1 |
|
T6 |
6 |
|
T56 |
1 |
|
T27 |
4 |
| others[1] |
104 |
1 |
|
T6 |
3 |
|
T27 |
4 |
|
T60 |
4 |
| others[2] |
109 |
1 |
|
T6 |
3 |
|
T27 |
1 |
|
T60 |
5 |
| others[3] |
167 |
1 |
|
T6 |
5 |
|
T16 |
1 |
|
T17 |
1 |
| false |
44 |
1 |
|
T27 |
7 |
|
T79 |
1 |
|
T95 |
2 |
| true |
6369 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T6 |
10 |
|
T27 |
10 |
|
T60 |
7 |
| others[1] |
226 |
1 |
|
T6 |
10 |
|
T17 |
1 |
|
T20 |
1 |
| others[2] |
225 |
1 |
|
T6 |
9 |
|
T27 |
11 |
|
T60 |
6 |
| others[3] |
402 |
1 |
|
T14 |
1 |
|
T6 |
12 |
|
T38 |
1 |
| false |
135 |
1 |
|
T6 |
6 |
|
T27 |
4 |
|
T60 |
5 |
| true |
5709 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1026 |
1 |
|
T6 |
21 |
|
T15 |
1 |
|
T38 |
1 |
| others[1] |
1101 |
1 |
|
T6 |
17 |
|
T91 |
1 |
|
T36 |
1 |
| others[2] |
1083 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
21 |
| others[3] |
1770 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T6 |
28 |
| false |
620 |
1 |
|
T6 |
14 |
|
T53 |
1 |
|
T27 |
11 |
| true |
1314 |
1 |
|
T16 |
1 |
|
T17 |
1 |
|
T20 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |