Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T6 |
9 |
|
T27 |
11 |
|
T60 |
6 |
| others[1] |
234 |
1 |
|
T6 |
7 |
|
T27 |
13 |
|
T60 |
15 |
| others[2] |
226 |
1 |
|
T6 |
8 |
|
T56 |
1 |
|
T27 |
7 |
| others[3] |
395 |
1 |
|
T6 |
20 |
|
T17 |
1 |
|
T27 |
12 |
| false |
117 |
1 |
|
T6 |
2 |
|
T56 |
1 |
|
T36 |
1 |
| true |
5726 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T6 |
10 |
|
T27 |
5 |
|
T60 |
5 |
| others[1] |
228 |
1 |
|
T6 |
14 |
|
T27 |
15 |
|
T60 |
8 |
| others[2] |
230 |
1 |
|
T6 |
7 |
|
T38 |
1 |
|
T27 |
12 |
| others[3] |
362 |
1 |
|
T6 |
12 |
|
T32 |
1 |
|
T27 |
17 |
| false |
93 |
1 |
|
T6 |
4 |
|
T56 |
1 |
|
T27 |
4 |
| true |
5796 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T2 |
1 |
|
T6 |
17 |
|
T36 |
1 |
| others[1] |
1291 |
1 |
|
T6 |
16 |
|
T38 |
1 |
|
T18 |
1 |
| others[2] |
1287 |
1 |
|
T5 |
1 |
|
T6 |
17 |
|
T15 |
1 |
| others[3] |
2105 |
1 |
|
T1 |
1 |
|
T6 |
39 |
|
T56 |
2 |
| false |
640 |
1 |
|
T6 |
12 |
|
T27 |
9 |
|
T60 |
11 |
| true |
360 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T2 |
1 |
|
T6 |
18 |
|
T27 |
19 |
| others[1] |
1252 |
1 |
|
T6 |
20 |
|
T27 |
13 |
|
T60 |
15 |
| others[2] |
1294 |
1 |
|
T5 |
1 |
|
T6 |
26 |
|
T15 |
1 |
| others[3] |
2166 |
1 |
|
T6 |
30 |
|
T38 |
1 |
|
T18 |
1 |
| false |
665 |
1 |
|
T1 |
1 |
|
T6 |
7 |
|
T53 |
1 |
| true |
333 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T6 |
4 |
|
T27 |
5 |
|
T60 |
5 |
| others[1] |
97 |
1 |
|
T6 |
4 |
|
T27 |
6 |
|
T60 |
2 |
| others[2] |
93 |
1 |
|
T6 |
2 |
|
T27 |
3 |
|
T60 |
1 |
| others[3] |
150 |
1 |
|
T6 |
7 |
|
T56 |
1 |
|
T36 |
1 |
| false |
69 |
1 |
|
T6 |
1 |
|
T56 |
1 |
|
T27 |
2 |
| true |
6397 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T6 |
14 |
|
T56 |
1 |
|
T27 |
16 |
| others[1] |
208 |
1 |
|
T6 |
7 |
|
T20 |
1 |
|
T27 |
4 |
| others[2] |
226 |
1 |
|
T6 |
11 |
|
T38 |
1 |
|
T27 |
5 |
| others[3] |
355 |
1 |
|
T6 |
15 |
|
T27 |
18 |
|
T60 |
14 |
| false |
111 |
1 |
|
T6 |
7 |
|
T27 |
2 |
|
T60 |
5 |
| true |
5772 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T6 |
15 |
|
T15 |
1 |
|
T17 |
1 |
| others[1] |
1050 |
1 |
|
T2 |
1 |
|
T6 |
20 |
|
T53 |
1 |
| others[2] |
1063 |
1 |
|
T14 |
1 |
|
T5 |
1 |
|
T6 |
23 |
| others[3] |
1818 |
1 |
|
T1 |
1 |
|
T6 |
32 |
|
T18 |
1 |
| false |
559 |
1 |
|
T6 |
11 |
|
T20 |
1 |
|
T27 |
11 |
| true |
1361 |
1 |
|
T16 |
1 |
|
T38 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T6 |
11 |
|
T16 |
1 |
|
T36 |
1 |
| others[1] |
196 |
1 |
|
T6 |
6 |
|
T27 |
7 |
|
T60 |
9 |
| others[2] |
213 |
1 |
|
T6 |
12 |
|
T27 |
6 |
|
T60 |
10 |
| others[3] |
381 |
1 |
|
T6 |
21 |
|
T17 |
1 |
|
T38 |
1 |
| false |
112 |
1 |
|
T6 |
2 |
|
T27 |
5 |
|
T60 |
4 |
| true |
5787 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T6 |
7 |
|
T38 |
1 |
|
T27 |
11 |
| others[1] |
208 |
1 |
|
T6 |
11 |
|
T27 |
8 |
|
T86 |
1 |
| others[2] |
222 |
1 |
|
T6 |
8 |
|
T16 |
1 |
|
T36 |
1 |
| others[3] |
360 |
1 |
|
T6 |
17 |
|
T17 |
1 |
|
T32 |
1 |
| false |
104 |
1 |
|
T6 |
2 |
|
T27 |
4 |
|
T60 |
1 |
| true |
5776 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1292 |
1 |
|
T5 |
1 |
|
T6 |
15 |
|
T27 |
26 |
| others[1] |
1293 |
1 |
|
T6 |
25 |
|
T56 |
1 |
|
T36 |
1 |
| others[2] |
1190 |
1 |
|
T1 |
1 |
|
T6 |
25 |
|
T15 |
1 |
| others[3] |
2117 |
1 |
|
T2 |
1 |
|
T6 |
30 |
|
T56 |
1 |
| false |
672 |
1 |
|
T6 |
6 |
|
T18 |
1 |
|
T53 |
1 |
| true |
350 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T2 |
1 |
|
T6 |
23 |
|
T18 |
1 |
| others[1] |
1264 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
21 |
| others[2] |
1272 |
1 |
|
T6 |
16 |
|
T53 |
1 |
|
T27 |
23 |
| others[3] |
2179 |
1 |
|
T6 |
30 |
|
T15 |
1 |
|
T91 |
1 |
| false |
627 |
1 |
|
T6 |
11 |
|
T56 |
1 |
|
T27 |
7 |
| true |
332 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T6 |
4 |
|
T56 |
2 |
|
T27 |
6 |
| others[1] |
103 |
1 |
|
T6 |
1 |
|
T27 |
1 |
|
T60 |
2 |
| others[2] |
97 |
1 |
|
T6 |
6 |
|
T36 |
1 |
|
T27 |
5 |
| others[3] |
166 |
1 |
|
T6 |
5 |
|
T27 |
6 |
|
T60 |
9 |
| false |
55 |
1 |
|
T6 |
1 |
|
T60 |
4 |
|
T79 |
1 |
| true |
6377 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T6 |
9 |
|
T16 |
1 |
|
T38 |
1 |
| others[1] |
247 |
1 |
|
T6 |
12 |
|
T17 |
1 |
|
T56 |
1 |
| others[2] |
246 |
1 |
|
T6 |
10 |
|
T36 |
1 |
|
T27 |
13 |
| others[3] |
377 |
1 |
|
T6 |
19 |
|
T27 |
15 |
|
T86 |
1 |
| false |
139 |
1 |
|
T6 |
3 |
|
T60 |
4 |
|
T79 |
7 |
| true |
5670 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1052 |
1 |
|
T6 |
16 |
|
T91 |
1 |
|
T27 |
23 |
| others[1] |
1118 |
1 |
|
T6 |
25 |
|
T16 |
1 |
|
T20 |
1 |
| others[2] |
1116 |
1 |
|
T5 |
1 |
|
T6 |
23 |
|
T17 |
1 |
| others[3] |
1743 |
1 |
|
T1 |
1 |
|
T6 |
26 |
|
T15 |
1 |
| false |
567 |
1 |
|
T2 |
1 |
|
T6 |
11 |
|
T10 |
1 |
| true |
1318 |
1 |
|
T14 |
1 |
|
T38 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T6 |
9 |
|
T27 |
9 |
|
T60 |
10 |
| others[1] |
245 |
1 |
|
T6 |
16 |
|
T17 |
1 |
|
T27 |
14 |
| others[2] |
221 |
1 |
|
T6 |
12 |
|
T27 |
5 |
|
T60 |
6 |
| others[3] |
378 |
1 |
|
T6 |
12 |
|
T27 |
19 |
|
T60 |
16 |
| false |
132 |
1 |
|
T6 |
6 |
|
T56 |
1 |
|
T27 |
5 |
| true |
5726 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T6 |
12 |
|
T38 |
1 |
|
T27 |
8 |
| others[1] |
194 |
1 |
|
T6 |
15 |
|
T16 |
1 |
|
T17 |
1 |
| others[2] |
210 |
1 |
|
T6 |
9 |
|
T56 |
1 |
|
T27 |
10 |
| others[3] |
371 |
1 |
|
T6 |
14 |
|
T36 |
1 |
|
T27 |
19 |
| false |
95 |
1 |
|
T6 |
3 |
|
T27 |
3 |
|
T60 |
4 |
| true |
5828 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T5 |
1 |
|
T6 |
22 |
|
T32 |
1 |
| others[1] |
1287 |
1 |
|
T6 |
21 |
|
T27 |
12 |
|
T60 |
27 |
| others[2] |
1272 |
1 |
|
T6 |
26 |
|
T27 |
23 |
|
T21 |
1 |
| others[3] |
2154 |
1 |
|
T1 |
1 |
|
T6 |
22 |
|
T15 |
1 |
| false |
593 |
1 |
|
T2 |
1 |
|
T6 |
10 |
|
T36 |
1 |
| true |
351 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1296 |
1 |
|
T6 |
18 |
|
T27 |
21 |
|
T60 |
30 |
| others[1] |
1259 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
25 |
| others[2] |
1282 |
1 |
|
T5 |
1 |
|
T6 |
17 |
|
T36 |
1 |
| others[3] |
2123 |
1 |
|
T6 |
26 |
|
T15 |
1 |
|
T91 |
1 |
| false |
636 |
1 |
|
T6 |
15 |
|
T56 |
1 |
|
T27 |
9 |
| true |
318 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T6 |
2 |
|
T27 |
4 |
|
T60 |
3 |
| others[1] |
94 |
1 |
|
T6 |
2 |
|
T56 |
1 |
|
T36 |
1 |
| others[2] |
115 |
1 |
|
T6 |
3 |
|
T56 |
1 |
|
T27 |
1 |
| others[3] |
157 |
1 |
|
T6 |
5 |
|
T27 |
5 |
|
T60 |
4 |
| false |
55 |
1 |
|
T6 |
2 |
|
T27 |
5 |
|
T60 |
3 |
| true |
6383 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T6 |
10 |
|
T17 |
1 |
|
T38 |
1 |
| others[1] |
250 |
1 |
|
T6 |
14 |
|
T36 |
1 |
|
T27 |
14 |
| others[2] |
230 |
1 |
|
T6 |
11 |
|
T27 |
7 |
|
T60 |
5 |
| others[3] |
364 |
1 |
|
T14 |
1 |
|
T6 |
11 |
|
T32 |
1 |
| false |
139 |
1 |
|
T6 |
7 |
|
T56 |
1 |
|
T27 |
6 |
| true |
5722 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1033 |
1 |
|
T6 |
26 |
|
T38 |
1 |
|
T91 |
1 |
| others[1] |
1034 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
19 |
| others[2] |
1085 |
1 |
|
T6 |
21 |
|
T36 |
1 |
|
T27 |
18 |
| others[3] |
1869 |
1 |
|
T6 |
28 |
|
T15 |
1 |
|
T56 |
1 |
| false |
576 |
1 |
|
T1 |
1 |
|
T6 |
7 |
|
T27 |
10 |
| true |
1317 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T6 |
6 |
|
T27 |
16 |
|
T60 |
11 |
| others[1] |
218 |
1 |
|
T6 |
9 |
|
T16 |
1 |
|
T27 |
11 |
| others[2] |
215 |
1 |
|
T6 |
14 |
|
T27 |
8 |
|
T60 |
5 |
| others[3] |
351 |
1 |
|
T6 |
15 |
|
T38 |
1 |
|
T56 |
1 |
| false |
106 |
1 |
|
T6 |
2 |
|
T32 |
1 |
|
T56 |
1 |
| true |
5772 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T6 |
8 |
|
T27 |
9 |
|
T60 |
9 |
| others[1] |
223 |
1 |
|
T6 |
15 |
|
T17 |
1 |
|
T27 |
8 |
| others[2] |
212 |
1 |
|
T6 |
13 |
|
T32 |
1 |
|
T27 |
13 |
| others[3] |
382 |
1 |
|
T6 |
21 |
|
T36 |
1 |
|
T27 |
16 |
| false |
120 |
1 |
|
T6 |
3 |
|
T38 |
1 |
|
T27 |
7 |
| true |
5772 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1307 |
1 |
|
T6 |
16 |
|
T56 |
1 |
|
T54 |
1 |
| others[1] |
1252 |
1 |
|
T6 |
22 |
|
T36 |
1 |
|
T27 |
10 |
| others[2] |
1228 |
1 |
|
T6 |
18 |
|
T15 |
1 |
|
T91 |
1 |
| others[3] |
2133 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
35 |
| false |
645 |
1 |
|
T2 |
1 |
|
T6 |
10 |
|
T38 |
1 |
| true |
349 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T6 |
19 |
|
T15 |
1 |
|
T27 |
19 |
| others[1] |
1289 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
24 |
| others[2] |
1244 |
1 |
|
T2 |
1 |
|
T6 |
15 |
|
T56 |
1 |
| others[3] |
2182 |
1 |
|
T6 |
34 |
|
T56 |
1 |
|
T53 |
1 |
| false |
639 |
1 |
|
T6 |
9 |
|
T36 |
1 |
|
T27 |
6 |
| true |
333 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T6 |
5 |
|
T27 |
9 |
|
T60 |
5 |
| others[1] |
87 |
1 |
|
T6 |
7 |
|
T27 |
4 |
|
T60 |
2 |
| others[2] |
83 |
1 |
|
T6 |
4 |
|
T36 |
1 |
|
T27 |
3 |
| others[3] |
171 |
1 |
|
T6 |
9 |
|
T56 |
2 |
|
T27 |
3 |
| false |
56 |
1 |
|
T27 |
2 |
|
T60 |
3 |
|
T79 |
1 |
| true |
6408 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T6 |
6 |
|
T17 |
1 |
|
T27 |
10 |
| others[1] |
217 |
1 |
|
T6 |
9 |
|
T27 |
10 |
|
T60 |
6 |
| others[2] |
233 |
1 |
|
T6 |
6 |
|
T27 |
10 |
|
T60 |
13 |
| others[3] |
344 |
1 |
|
T14 |
1 |
|
T6 |
18 |
|
T38 |
1 |
| false |
117 |
1 |
|
T6 |
7 |
|
T20 |
1 |
|
T27 |
9 |
| true |
5792 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1106 |
1 |
|
T14 |
1 |
|
T6 |
21 |
|
T27 |
17 |
| others[1] |
1074 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
14 |
| others[2] |
1073 |
1 |
|
T1 |
1 |
|
T6 |
19 |
|
T16 |
1 |
| others[3] |
1752 |
1 |
|
T6 |
36 |
|
T91 |
1 |
|
T56 |
1 |
| false |
572 |
1 |
|
T6 |
11 |
|
T36 |
1 |
|
T27 |
13 |
| true |
1337 |
1 |
|
T38 |
1 |
|
T32 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T6 |
12 |
|
T27 |
8 |
|
T60 |
10 |
| others[1] |
219 |
1 |
|
T6 |
12 |
|
T27 |
16 |
|
T60 |
9 |
| others[2] |
220 |
1 |
|
T6 |
12 |
|
T27 |
15 |
|
T60 |
9 |
| others[3] |
355 |
1 |
|
T6 |
10 |
|
T17 |
1 |
|
T38 |
1 |
| false |
123 |
1 |
|
T6 |
9 |
|
T32 |
1 |
|
T27 |
2 |
| true |
5768 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T6 |
8 |
|
T27 |
11 |
|
T60 |
16 |
| others[1] |
191 |
1 |
|
T6 |
7 |
|
T27 |
8 |
|
T60 |
10 |
| others[2] |
222 |
1 |
|
T6 |
15 |
|
T32 |
1 |
|
T56 |
1 |
| others[3] |
373 |
1 |
|
T6 |
12 |
|
T17 |
1 |
|
T36 |
1 |
| false |
129 |
1 |
|
T6 |
8 |
|
T27 |
6 |
|
T60 |
6 |
| true |
5766 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T1 |
1 |
|
T6 |
19 |
|
T56 |
1 |
| others[1] |
1253 |
1 |
|
T6 |
13 |
|
T53 |
1 |
|
T27 |
28 |
| others[2] |
1216 |
1 |
|
T6 |
26 |
|
T91 |
1 |
|
T56 |
1 |
| others[3] |
2158 |
1 |
|
T5 |
1 |
|
T6 |
33 |
|
T15 |
1 |
| false |
657 |
1 |
|
T2 |
1 |
|
T6 |
10 |
|
T18 |
1 |
| true |
357 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |