Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1276 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
19 |
| others[1] |
1305 |
1 |
|
T6 |
18 |
|
T15 |
1 |
|
T56 |
1 |
| others[2] |
1223 |
1 |
|
T6 |
17 |
|
T27 |
15 |
|
T60 |
18 |
| others[3] |
2108 |
1 |
|
T6 |
38 |
|
T18 |
1 |
|
T91 |
1 |
| false |
668 |
1 |
|
T5 |
1 |
|
T6 |
9 |
|
T27 |
12 |
| true |
334 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T6 |
4 |
|
T27 |
3 |
|
T60 |
2 |
| others[1] |
100 |
1 |
|
T6 |
5 |
|
T27 |
6 |
|
T60 |
5 |
| others[2] |
127 |
1 |
|
T6 |
3 |
|
T56 |
1 |
|
T27 |
4 |
| others[3] |
162 |
1 |
|
T6 |
6 |
|
T56 |
1 |
|
T36 |
1 |
| false |
53 |
1 |
|
T6 |
5 |
|
T27 |
1 |
|
T60 |
3 |
| true |
6374 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T6 |
16 |
|
T56 |
2 |
|
T27 |
6 |
| others[1] |
238 |
1 |
|
T6 |
17 |
|
T20 |
1 |
|
T27 |
10 |
| others[2] |
221 |
1 |
|
T6 |
8 |
|
T27 |
10 |
|
T60 |
10 |
| others[3] |
392 |
1 |
|
T6 |
14 |
|
T27 |
19 |
|
T86 |
1 |
| false |
125 |
1 |
|
T6 |
5 |
|
T27 |
4 |
|
T60 |
4 |
| true |
5711 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T6 |
20 |
|
T52 |
1 |
|
T27 |
25 |
| others[1] |
1086 |
1 |
|
T6 |
32 |
|
T27 |
15 |
|
T60 |
25 |
| others[2] |
1080 |
1 |
|
T6 |
15 |
|
T10 |
1 |
|
T91 |
1 |
| others[3] |
1738 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| false |
520 |
1 |
|
T6 |
7 |
|
T53 |
1 |
|
T36 |
1 |
| true |
1420 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T6 |
10 |
|
T27 |
8 |
|
T86 |
1 |
| others[1] |
206 |
1 |
|
T6 |
7 |
|
T16 |
1 |
|
T27 |
11 |
| others[2] |
236 |
1 |
|
T6 |
12 |
|
T38 |
1 |
|
T27 |
9 |
| others[3] |
387 |
1 |
|
T6 |
14 |
|
T17 |
1 |
|
T27 |
13 |
| false |
118 |
1 |
|
T6 |
1 |
|
T56 |
1 |
|
T36 |
1 |
| true |
5744 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T6 |
6 |
|
T56 |
1 |
|
T27 |
11 |
| others[1] |
205 |
1 |
|
T6 |
11 |
|
T27 |
9 |
|
T60 |
7 |
| others[2] |
224 |
1 |
|
T6 |
10 |
|
T27 |
8 |
|
T86 |
1 |
| others[3] |
354 |
1 |
|
T6 |
18 |
|
T38 |
1 |
|
T27 |
16 |
| false |
110 |
1 |
|
T6 |
3 |
|
T27 |
4 |
|
T60 |
3 |
| true |
5808 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T6 |
21 |
|
T56 |
1 |
|
T27 |
15 |
| others[1] |
1306 |
1 |
|
T6 |
18 |
|
T15 |
1 |
|
T56 |
1 |
| others[2] |
1215 |
1 |
|
T1 |
1 |
|
T6 |
21 |
|
T27 |
19 |
| others[3] |
2100 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
29 |
| false |
688 |
1 |
|
T6 |
12 |
|
T27 |
13 |
|
T60 |
14 |
| true |
369 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T1 |
1 |
|
T6 |
22 |
|
T53 |
1 |
| others[1] |
1263 |
1 |
|
T6 |
18 |
|
T15 |
1 |
|
T56 |
1 |
| others[2] |
1333 |
1 |
|
T6 |
28 |
|
T18 |
1 |
|
T91 |
1 |
| others[3] |
2097 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
25 |
| false |
628 |
1 |
|
T6 |
8 |
|
T27 |
6 |
|
T60 |
6 |
| true |
328 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T6 |
4 |
|
T27 |
3 |
|
T60 |
6 |
| others[1] |
103 |
1 |
|
T6 |
1 |
|
T56 |
1 |
|
T27 |
4 |
| others[2] |
102 |
1 |
|
T6 |
4 |
|
T56 |
1 |
|
T27 |
5 |
| others[3] |
147 |
1 |
|
T6 |
3 |
|
T27 |
10 |
|
T60 |
6 |
| false |
49 |
1 |
|
T6 |
2 |
|
T36 |
1 |
|
T27 |
3 |
| true |
6397 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T6 |
15 |
|
T38 |
1 |
|
T56 |
1 |
| others[1] |
256 |
1 |
|
T6 |
6 |
|
T17 |
1 |
|
T27 |
11 |
| others[2] |
221 |
1 |
|
T6 |
10 |
|
T32 |
1 |
|
T27 |
11 |
| others[3] |
347 |
1 |
|
T6 |
13 |
|
T27 |
17 |
|
T60 |
13 |
| false |
128 |
1 |
|
T6 |
6 |
|
T20 |
1 |
|
T56 |
1 |
| true |
5755 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1077 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
20 |
| others[1] |
1111 |
1 |
|
T2 |
1 |
|
T6 |
18 |
|
T15 |
1 |
| others[2] |
1049 |
1 |
|
T6 |
22 |
|
T53 |
1 |
|
T27 |
16 |
| others[3] |
1858 |
1 |
|
T6 |
35 |
|
T18 |
1 |
|
T56 |
2 |
| false |
500 |
1 |
|
T6 |
6 |
|
T20 |
1 |
|
T27 |
11 |
| true |
1319 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T6 |
5 |
|
T17 |
1 |
|
T27 |
8 |
| others[1] |
224 |
1 |
|
T6 |
10 |
|
T16 |
1 |
|
T20 |
1 |
| others[2] |
227 |
1 |
|
T6 |
9 |
|
T56 |
1 |
|
T27 |
16 |
| others[3] |
358 |
1 |
|
T6 |
17 |
|
T32 |
1 |
|
T36 |
1 |
| false |
117 |
1 |
|
T6 |
5 |
|
T38 |
1 |
|
T27 |
5 |
| true |
5777 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
203 |
1 |
|
T6 |
8 |
|
T27 |
7 |
|
T60 |
9 |
| others[1] |
224 |
1 |
|
T6 |
11 |
|
T27 |
16 |
|
T60 |
8 |
| others[2] |
216 |
1 |
|
T6 |
9 |
|
T32 |
1 |
|
T27 |
9 |
| others[3] |
384 |
1 |
|
T6 |
16 |
|
T36 |
1 |
|
T27 |
21 |
| false |
100 |
1 |
|
T6 |
3 |
|
T27 |
5 |
|
T60 |
6 |
| true |
5787 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1313 |
1 |
|
T6 |
15 |
|
T56 |
2 |
|
T27 |
16 |
| others[1] |
1255 |
1 |
|
T6 |
21 |
|
T18 |
1 |
|
T27 |
18 |
| others[2] |
1206 |
1 |
|
T6 |
17 |
|
T91 |
1 |
|
T53 |
1 |
| others[3] |
2140 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| false |
647 |
1 |
|
T6 |
11 |
|
T38 |
1 |
|
T27 |
16 |
| true |
353 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T6 |
16 |
|
T27 |
16 |
|
T60 |
12 |
| others[1] |
1295 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
19 |
| others[2] |
1279 |
1 |
|
T2 |
1 |
|
T6 |
21 |
|
T53 |
1 |
| others[3] |
2088 |
1 |
|
T6 |
32 |
|
T15 |
1 |
|
T18 |
1 |
| false |
650 |
1 |
|
T6 |
13 |
|
T27 |
12 |
|
T60 |
8 |
| true |
337 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T6 |
8 |
|
T36 |
1 |
|
T27 |
2 |
| others[1] |
112 |
1 |
|
T6 |
5 |
|
T56 |
1 |
|
T27 |
6 |
| others[2] |
116 |
1 |
|
T6 |
5 |
|
T27 |
6 |
|
T60 |
3 |
| others[3] |
152 |
1 |
|
T6 |
8 |
|
T56 |
1 |
|
T27 |
8 |
| false |
69 |
1 |
|
T6 |
1 |
|
T27 |
3 |
|
T60 |
4 |
| true |
6370 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T14 |
1 |
|
T6 |
10 |
|
T16 |
1 |
| others[1] |
192 |
1 |
|
T6 |
11 |
|
T32 |
1 |
|
T20 |
1 |
| others[2] |
231 |
1 |
|
T6 |
15 |
|
T27 |
11 |
|
T60 |
12 |
| others[3] |
375 |
1 |
|
T6 |
14 |
|
T17 |
1 |
|
T27 |
18 |
| false |
119 |
1 |
|
T6 |
2 |
|
T27 |
3 |
|
T86 |
1 |
| true |
5758 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1098 |
1 |
|
T6 |
25 |
|
T38 |
1 |
|
T18 |
1 |
| others[1] |
1065 |
1 |
|
T5 |
1 |
|
T6 |
17 |
|
T91 |
1 |
| others[2] |
1078 |
1 |
|
T6 |
24 |
|
T56 |
1 |
|
T27 |
18 |
| others[3] |
1776 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
28 |
| false |
556 |
1 |
|
T6 |
7 |
|
T36 |
1 |
|
T27 |
11 |
| true |
1341 |
1 |
|
T14 |
1 |
|
T32 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T6 |
15 |
|
T32 |
1 |
|
T27 |
6 |
| others[1] |
234 |
1 |
|
T6 |
6 |
|
T16 |
1 |
|
T27 |
19 |
| others[2] |
221 |
1 |
|
T6 |
7 |
|
T20 |
1 |
|
T27 |
12 |
| others[3] |
376 |
1 |
|
T6 |
15 |
|
T56 |
2 |
|
T36 |
1 |
| false |
118 |
1 |
|
T6 |
3 |
|
T27 |
8 |
|
T60 |
3 |
| true |
5733 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T6 |
9 |
|
T38 |
1 |
|
T56 |
1 |
| others[1] |
211 |
1 |
|
T6 |
8 |
|
T17 |
1 |
|
T36 |
1 |
| others[2] |
216 |
1 |
|
T6 |
8 |
|
T27 |
10 |
|
T60 |
14 |
| others[3] |
384 |
1 |
|
T6 |
14 |
|
T27 |
16 |
|
T60 |
19 |
| false |
95 |
1 |
|
T6 |
4 |
|
T27 |
6 |
|
T60 |
8 |
| true |
5778 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1277 |
1 |
|
T5 |
1 |
|
T6 |
21 |
|
T15 |
1 |
| others[1] |
1278 |
1 |
|
T6 |
15 |
|
T18 |
1 |
|
T91 |
1 |
| others[2] |
1265 |
1 |
|
T6 |
16 |
|
T56 |
1 |
|
T36 |
1 |
| others[3] |
2144 |
1 |
|
T1 |
1 |
|
T6 |
42 |
|
T32 |
1 |
| false |
601 |
1 |
|
T2 |
1 |
|
T6 |
7 |
|
T27 |
5 |
| true |
349 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1289 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
28 |
| others[1] |
1327 |
1 |
|
T1 |
1 |
|
T6 |
17 |
|
T56 |
1 |
| others[2] |
1306 |
1 |
|
T6 |
15 |
|
T27 |
20 |
|
T60 |
24 |
| others[3] |
2022 |
1 |
|
T6 |
34 |
|
T15 |
1 |
|
T18 |
1 |
| false |
638 |
1 |
|
T6 |
7 |
|
T27 |
12 |
|
T60 |
9 |
| true |
332 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T6 |
7 |
|
T27 |
4 |
|
T60 |
4 |
| others[1] |
95 |
1 |
|
T6 |
2 |
|
T36 |
1 |
|
T27 |
2 |
| others[2] |
101 |
1 |
|
T6 |
1 |
|
T17 |
1 |
|
T27 |
4 |
| others[3] |
177 |
1 |
|
T6 |
7 |
|
T56 |
2 |
|
T27 |
6 |
| false |
49 |
1 |
|
T6 |
6 |
|
T27 |
3 |
|
T60 |
1 |
| true |
6384 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T6 |
12 |
|
T27 |
6 |
|
T60 |
9 |
| others[1] |
215 |
1 |
|
T6 |
9 |
|
T38 |
1 |
|
T56 |
1 |
| others[2] |
241 |
1 |
|
T6 |
11 |
|
T27 |
8 |
|
T60 |
8 |
| others[3] |
411 |
1 |
|
T6 |
16 |
|
T32 |
1 |
|
T20 |
1 |
| false |
114 |
1 |
|
T6 |
3 |
|
T27 |
5 |
|
T60 |
2 |
| true |
5722 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1104 |
1 |
|
T6 |
16 |
|
T17 |
1 |
|
T27 |
23 |
| others[1] |
1071 |
1 |
|
T5 |
1 |
|
T6 |
16 |
|
T16 |
1 |
| others[2] |
1007 |
1 |
|
T2 |
1 |
|
T6 |
20 |
|
T15 |
1 |
| others[3] |
1842 |
1 |
|
T6 |
37 |
|
T20 |
1 |
|
T91 |
1 |
| false |
560 |
1 |
|
T1 |
1 |
|
T6 |
12 |
|
T56 |
2 |
| true |
1330 |
1 |
|
T14 |
1 |
|
T38 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T6 |
7 |
|
T32 |
1 |
|
T56 |
1 |
| others[1] |
181 |
1 |
|
T6 |
9 |
|
T27 |
9 |
|
T60 |
6 |
| others[2] |
207 |
1 |
|
T6 |
18 |
|
T27 |
17 |
|
T60 |
7 |
| others[3] |
396 |
1 |
|
T6 |
18 |
|
T17 |
1 |
|
T36 |
1 |
| false |
122 |
1 |
|
T6 |
6 |
|
T27 |
6 |
|
T60 |
4 |
| true |
5758 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T6 |
8 |
|
T36 |
1 |
|
T27 |
7 |
| others[1] |
208 |
1 |
|
T6 |
9 |
|
T27 |
6 |
|
T60 |
9 |
| others[2] |
193 |
1 |
|
T6 |
10 |
|
T27 |
9 |
|
T60 |
6 |
| others[3] |
393 |
1 |
|
T6 |
20 |
|
T38 |
1 |
|
T27 |
20 |
| false |
115 |
1 |
|
T6 |
4 |
|
T56 |
1 |
|
T27 |
5 |
| true |
5787 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1271 |
1 |
|
T6 |
17 |
|
T91 |
1 |
|
T56 |
1 |
| others[1] |
1223 |
1 |
|
T6 |
21 |
|
T54 |
1 |
|
T27 |
17 |
| others[2] |
1311 |
1 |
|
T6 |
18 |
|
T18 |
1 |
|
T27 |
17 |
| others[3] |
2092 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| false |
675 |
1 |
|
T6 |
15 |
|
T27 |
11 |
|
T21 |
1 |
| true |
342 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T154 |
1 |
|
T138 |
1 |
|
T378 |
1 |
| others[1] |
5 |
1 |
|
T3 |
1 |
|
T68 |
1 |
|
T69 |
1 |
| others[2] |
14 |
1 |
|
T52 |
1 |
|
T68 |
1 |
|
T63 |
1 |
| others[3] |
14 |
1 |
|
T153 |
1 |
|
T379 |
1 |
|
T380 |
1 |
| false |
7 |
1 |
|
T55 |
1 |
|
T283 |
1 |
|
T381 |
1 |
| true |
50 |
1 |
|
T10 |
1 |
|
T11 |
1 |
|
T68 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T382 |
1 |
|
T383 |
1 |
|
- |
- |
| others[1] |
4 |
1 |
|
T384 |
1 |
|
T385 |
1 |
|
T386 |
1 |
| others[2] |
4 |
1 |
|
T387 |
1 |
|
T388 |
1 |
|
T389 |
1 |
| others[3] |
6 |
1 |
|
T26 |
1 |
|
T390 |
1 |
|
T391 |
1 |
| false |
11 |
1 |
|
T37 |
1 |
|
T246 |
1 |
|
T162 |
1 |
| true |
21 |
1 |
|
T161 |
1 |
|
T392 |
1 |
|
T393 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T37 |
1 |
|
T394 |
1 |
|
T395 |
1 |
| others[1] |
6 |
1 |
|
T161 |
1 |
|
T162 |
1 |
|
T396 |
1 |
| others[2] |
2 |
1 |
|
T246 |
1 |
|
T397 |
1 |
|
- |
- |
| others[3] |
3 |
1 |
|
T392 |
1 |
|
T398 |
1 |
|
T399 |
1 |
| false |
7 |
1 |
|
T384 |
1 |
|
T400 |
1 |
|
T385 |
1 |
| true |
25 |
1 |
|
T26 |
1 |
|
T393 |
1 |
|
T401 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |