Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9353 |
1 |
|
T4 |
211 |
|
T5 |
1 |
|
T6 |
15 |
| others[1] |
790 |
1 |
|
T6 |
17 |
|
T27 |
20 |
|
T60 |
18 |
| others[2] |
815 |
1 |
|
T1 |
1 |
|
T6 |
25 |
|
T91 |
1 |
| others[3] |
1428 |
1 |
|
T6 |
33 |
|
T27 |
40 |
|
T60 |
37 |
| false |
378 |
1 |
|
T2 |
1 |
|
T6 |
11 |
|
T27 |
3 |
| true |
434 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2327 |
1 |
|
T4 |
38 |
|
T5 |
1 |
|
T6 |
11 |
| others[1] |
2282 |
1 |
|
T4 |
41 |
|
T6 |
9 |
|
T15 |
1 |
| others[2] |
2271 |
1 |
|
T4 |
42 |
|
T6 |
10 |
|
T18 |
1 |
| others[3] |
3680 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
68 |
| false |
1169 |
1 |
|
T4 |
22 |
|
T6 |
3 |
|
T42 |
4 |
| true |
1469 |
1 |
|
T14 |
1 |
|
T6 |
50 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8749 |
1 |
|
T4 |
211 |
|
T6 |
9 |
|
T15 |
1 |
| others[1] |
271 |
1 |
|
T6 |
9 |
|
T32 |
1 |
|
T27 |
8 |
| others[2] |
257 |
1 |
|
T6 |
15 |
|
T18 |
1 |
|
T91 |
1 |
| others[3] |
457 |
1 |
|
T14 |
1 |
|
T6 |
11 |
|
T27 |
19 |
| false |
124 |
1 |
|
T6 |
3 |
|
T27 |
4 |
|
T60 |
6 |
| true |
3340 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8975 |
1 |
|
T4 |
211 |
|
T6 |
15 |
|
T42 |
52 |
| others[1] |
482 |
1 |
|
T6 |
10 |
|
T27 |
11 |
|
T60 |
12 |
| others[2] |
484 |
1 |
|
T6 |
9 |
|
T32 |
1 |
|
T10 |
1 |
| others[3] |
785 |
1 |
|
T6 |
16 |
|
T15 |
1 |
|
T91 |
1 |
| false |
233 |
1 |
|
T2 |
1 |
|
T6 |
6 |
|
T27 |
6 |
| true |
2239 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8752 |
1 |
|
T4 |
211 |
|
T6 |
12 |
|
T42 |
52 |
| others[1] |
264 |
1 |
|
T2 |
1 |
|
T6 |
18 |
|
T38 |
1 |
| others[2] |
282 |
1 |
|
T6 |
9 |
|
T27 |
11 |
|
T60 |
13 |
| others[3] |
382 |
1 |
|
T5 |
1 |
|
T6 |
12 |
|
T18 |
1 |
| false |
139 |
1 |
|
T6 |
4 |
|
T27 |
6 |
|
T21 |
1 |
| true |
3379 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T6 |
46 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8752 |
1 |
|
T1 |
1 |
|
T4 |
211 |
|
T6 |
4 |
| others[1] |
246 |
1 |
|
T2 |
1 |
|
T6 |
9 |
|
T27 |
11 |
| others[2] |
239 |
1 |
|
T6 |
7 |
|
T36 |
1 |
|
T27 |
3 |
| others[3] |
425 |
1 |
|
T6 |
22 |
|
T16 |
1 |
|
T53 |
1 |
| false |
138 |
1 |
|
T6 |
5 |
|
T32 |
1 |
|
T27 |
4 |
| true |
3398 |
1 |
|
T14 |
1 |
|
T5 |
1 |
|
T6 |
54 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9344 |
1 |
|
T4 |
211 |
|
T6 |
11 |
|
T42 |
52 |
| others[1] |
887 |
1 |
|
T1 |
1 |
|
T6 |
21 |
|
T91 |
1 |
| others[2] |
773 |
1 |
|
T6 |
22 |
|
T15 |
1 |
|
T32 |
1 |
| others[3] |
1312 |
1 |
|
T5 |
1 |
|
T6 |
38 |
|
T18 |
1 |
| false |
439 |
1 |
|
T2 |
1 |
|
T6 |
9 |
|
T27 |
9 |
| true |
443 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9333 |
1 |
|
T4 |
211 |
|
T6 |
17 |
|
T18 |
1 |
| others[1] |
839 |
1 |
|
T2 |
1 |
|
T6 |
23 |
|
T15 |
1 |
| others[2] |
816 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
19 |
| others[3] |
1345 |
1 |
|
T6 |
30 |
|
T91 |
1 |
|
T53 |
1 |
| false |
405 |
1 |
|
T6 |
12 |
|
T56 |
1 |
|
T27 |
4 |
| true |
430 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2320 |
1 |
|
T2 |
1 |
|
T4 |
39 |
|
T6 |
11 |
| others[1] |
2267 |
1 |
|
T4 |
35 |
|
T6 |
12 |
|
T16 |
1 |
| others[2] |
2246 |
1 |
|
T4 |
48 |
|
T5 |
1 |
|
T6 |
7 |
| others[3] |
3727 |
1 |
|
T1 |
1 |
|
T4 |
70 |
|
T6 |
23 |
| false |
1153 |
1 |
|
T4 |
19 |
|
T6 |
8 |
|
T42 |
2 |
| true |
1455 |
1 |
|
T14 |
1 |
|
T6 |
40 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8779 |
1 |
|
T4 |
211 |
|
T6 |
9 |
|
T42 |
52 |
| others[1] |
290 |
1 |
|
T6 |
8 |
|
T91 |
1 |
|
T56 |
1 |
| others[2] |
229 |
1 |
|
T6 |
10 |
|
T27 |
8 |
|
T60 |
12 |
| others[3] |
449 |
1 |
|
T6 |
12 |
|
T16 |
1 |
|
T17 |
1 |
| false |
139 |
1 |
|
T6 |
8 |
|
T32 |
1 |
|
T20 |
1 |
| true |
3282 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8983 |
1 |
|
T4 |
211 |
|
T6 |
6 |
|
T42 |
52 |
| others[1] |
497 |
1 |
|
T6 |
7 |
|
T20 |
1 |
|
T56 |
1 |
| others[2] |
484 |
1 |
|
T5 |
1 |
|
T6 |
6 |
|
T56 |
1 |
| others[3] |
762 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T6 |
14 |
| false |
224 |
1 |
|
T6 |
5 |
|
T91 |
1 |
|
T27 |
6 |
| true |
2218 |
1 |
|
T2 |
1 |
|
T6 |
63 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8774 |
1 |
|
T4 |
211 |
|
T6 |
14 |
|
T42 |
52 |
| others[1] |
252 |
1 |
|
T6 |
12 |
|
T27 |
8 |
|
T60 |
9 |
| others[2] |
274 |
1 |
|
T2 |
1 |
|
T6 |
9 |
|
T27 |
12 |
| others[3] |
433 |
1 |
|
T6 |
12 |
|
T17 |
1 |
|
T56 |
1 |
| false |
135 |
1 |
|
T6 |
5 |
|
T38 |
1 |
|
T27 |
6 |
| true |
3300 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8744 |
1 |
|
T4 |
211 |
|
T6 |
14 |
|
T42 |
52 |
| others[1] |
241 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
11 |
| others[2] |
254 |
1 |
|
T6 |
12 |
|
T27 |
9 |
|
T21 |
1 |
| others[3] |
410 |
1 |
|
T1 |
1 |
|
T6 |
19 |
|
T91 |
1 |
| false |
129 |
1 |
|
T6 |
7 |
|
T27 |
1 |
|
T60 |
1 |
| true |
3390 |
1 |
|
T14 |
1 |
|
T6 |
38 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9279 |
1 |
|
T4 |
211 |
|
T6 |
18 |
|
T91 |
1 |
| others[1] |
801 |
1 |
|
T1 |
1 |
|
T6 |
18 |
|
T54 |
1 |
| others[2] |
856 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
21 |
| others[3] |
1406 |
1 |
|
T6 |
31 |
|
T32 |
1 |
|
T27 |
36 |
| false |
417 |
1 |
|
T6 |
13 |
|
T27 |
11 |
|
T60 |
13 |
| true |
409 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9332 |
1 |
|
T4 |
211 |
|
T6 |
24 |
|
T42 |
52 |
| others[1] |
794 |
1 |
|
T5 |
1 |
|
T6 |
21 |
|
T27 |
18 |
| others[2] |
790 |
1 |
|
T1 |
1 |
|
T6 |
20 |
|
T15 |
1 |
| others[3] |
1379 |
1 |
|
T2 |
1 |
|
T6 |
31 |
|
T36 |
1 |
| false |
441 |
1 |
|
T6 |
5 |
|
T18 |
1 |
|
T53 |
1 |
| true |
432 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2239 |
1 |
|
T4 |
38 |
|
T6 |
12 |
|
T42 |
11 |
| others[1] |
2301 |
1 |
|
T4 |
46 |
|
T6 |
10 |
|
T16 |
1 |
| others[2] |
2269 |
1 |
|
T4 |
48 |
|
T6 |
7 |
|
T15 |
1 |
| others[3] |
3660 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
60 |
| false |
1206 |
1 |
|
T4 |
19 |
|
T6 |
6 |
|
T42 |
6 |
| true |
1493 |
1 |
|
T14 |
1 |
|
T6 |
41 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8763 |
1 |
|
T2 |
1 |
|
T4 |
211 |
|
T6 |
10 |
| others[1] |
259 |
1 |
|
T5 |
1 |
|
T6 |
14 |
|
T17 |
1 |
| others[2] |
255 |
1 |
|
T6 |
10 |
|
T56 |
1 |
|
T27 |
7 |
| others[3] |
441 |
1 |
|
T6 |
18 |
|
T15 |
1 |
|
T91 |
1 |
| false |
132 |
1 |
|
T6 |
3 |
|
T27 |
3 |
|
T60 |
2 |
| true |
3318 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T6 |
46 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8965 |
1 |
|
T4 |
211 |
|
T6 |
11 |
|
T42 |
52 |
| others[1] |
486 |
1 |
|
T6 |
11 |
|
T17 |
1 |
|
T32 |
1 |
| others[2] |
483 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T6 |
9 |
| others[3] |
728 |
1 |
|
T6 |
14 |
|
T71 |
1 |
|
T27 |
12 |
| false |
243 |
1 |
|
T6 |
3 |
|
T16 |
1 |
|
T56 |
1 |
| true |
2263 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
53 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8738 |
1 |
|
T2 |
1 |
|
T4 |
211 |
|
T6 |
12 |
| others[1] |
264 |
1 |
|
T6 |
9 |
|
T17 |
1 |
|
T27 |
13 |
| others[2] |
227 |
1 |
|
T6 |
8 |
|
T91 |
1 |
|
T27 |
9 |
| others[3] |
406 |
1 |
|
T1 |
1 |
|
T6 |
13 |
|
T16 |
1 |
| false |
131 |
1 |
|
T5 |
1 |
|
T6 |
7 |
|
T27 |
6 |
| true |
3402 |
1 |
|
T14 |
1 |
|
T6 |
52 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8761 |
1 |
|
T4 |
211 |
|
T6 |
14 |
|
T42 |
52 |
| others[1] |
261 |
1 |
|
T6 |
10 |
|
T15 |
1 |
|
T16 |
1 |
| others[2] |
237 |
1 |
|
T1 |
1 |
|
T6 |
7 |
|
T27 |
7 |
| others[3] |
393 |
1 |
|
T6 |
14 |
|
T38 |
1 |
|
T18 |
1 |
| false |
130 |
1 |
|
T6 |
4 |
|
T27 |
7 |
|
T60 |
2 |
| true |
3386 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9329 |
1 |
|
T4 |
211 |
|
T6 |
16 |
|
T42 |
52 |
| others[1] |
794 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
17 |
| others[2] |
827 |
1 |
|
T6 |
15 |
|
T27 |
20 |
|
T60 |
18 |
| others[3] |
1398 |
1 |
|
T5 |
1 |
|
T6 |
39 |
|
T15 |
1 |
| false |
395 |
1 |
|
T6 |
14 |
|
T27 |
11 |
|
T60 |
6 |
| true |
425 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9309 |
1 |
|
T4 |
211 |
|
T6 |
18 |
|
T15 |
1 |
| others[1] |
818 |
1 |
|
T5 |
1 |
|
T6 |
18 |
|
T27 |
21 |
| others[2] |
819 |
1 |
|
T2 |
1 |
|
T6 |
29 |
|
T27 |
26 |
| others[3] |
1387 |
1 |
|
T1 |
1 |
|
T6 |
26 |
|
T18 |
1 |
| false |
389 |
1 |
|
T6 |
10 |
|
T27 |
5 |
|
T60 |
7 |
| true |
446 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2261 |
1 |
|
T2 |
1 |
|
T4 |
34 |
|
T5 |
1 |
| others[1] |
2237 |
1 |
|
T4 |
47 |
|
T6 |
15 |
|
T15 |
1 |
| others[2] |
2217 |
1 |
|
T4 |
40 |
|
T6 |
5 |
|
T91 |
1 |
| others[3] |
3774 |
1 |
|
T1 |
1 |
|
T4 |
68 |
|
T6 |
13 |
| false |
1194 |
1 |
|
T4 |
22 |
|
T6 |
6 |
|
T42 |
7 |
| true |
1485 |
1 |
|
T14 |
1 |
|
T6 |
57 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8752 |
1 |
|
T4 |
211 |
|
T6 |
5 |
|
T20 |
1 |
| others[1] |
258 |
1 |
|
T6 |
6 |
|
T27 |
6 |
|
T60 |
14 |
| others[2] |
262 |
1 |
|
T2 |
1 |
|
T6 |
11 |
|
T27 |
6 |
| others[3] |
446 |
1 |
|
T1 |
1 |
|
T6 |
16 |
|
T16 |
1 |
| false |
151 |
1 |
|
T6 |
2 |
|
T18 |
1 |
|
T27 |
6 |
| true |
3299 |
1 |
|
T14 |
1 |
|
T5 |
1 |
|
T6 |
61 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8961 |
1 |
|
T2 |
1 |
|
T4 |
211 |
|
T6 |
4 |
| others[1] |
467 |
1 |
|
T5 |
1 |
|
T6 |
6 |
|
T32 |
1 |
| others[2] |
467 |
1 |
|
T1 |
1 |
|
T6 |
12 |
|
T52 |
1 |
| others[3] |
820 |
1 |
|
T6 |
14 |
|
T56 |
2 |
|
T71 |
1 |
| false |
266 |
1 |
|
T6 |
8 |
|
T27 |
6 |
|
T60 |
8 |
| true |
2187 |
1 |
|
T14 |
1 |
|
T6 |
57 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8742 |
1 |
|
T4 |
211 |
|
T5 |
1 |
|
T6 |
13 |
| others[1] |
275 |
1 |
|
T2 |
1 |
|
T6 |
10 |
|
T20 |
1 |
| others[2] |
251 |
1 |
|
T6 |
11 |
|
T17 |
1 |
|
T53 |
1 |
| others[3] |
430 |
1 |
|
T6 |
18 |
|
T32 |
1 |
|
T56 |
1 |
| false |
136 |
1 |
|
T6 |
5 |
|
T16 |
1 |
|
T27 |
6 |
| true |
3334 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T6 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8736 |
1 |
|
T4 |
211 |
|
T6 |
9 |
|
T42 |
52 |
| others[1] |
225 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T56 |
1 |
| others[2] |
251 |
1 |
|
T6 |
9 |
|
T18 |
1 |
|
T27 |
12 |
| others[3] |
401 |
1 |
|
T2 |
1 |
|
T6 |
17 |
|
T53 |
1 |
| false |
148 |
1 |
|
T6 |
5 |
|
T38 |
1 |
|
T27 |
8 |
| true |
3407 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T6 |
56 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9355 |
1 |
|
T4 |
211 |
|
T6 |
24 |
|
T42 |
52 |
| others[1] |
819 |
1 |
|
T6 |
20 |
|
T15 |
1 |
|
T54 |
1 |
| others[2] |
814 |
1 |
|
T2 |
1 |
|
T6 |
14 |
|
T18 |
1 |
| others[3] |
1331 |
1 |
|
T5 |
1 |
|
T6 |
29 |
|
T27 |
38 |
| false |
420 |
1 |
|
T1 |
1 |
|
T6 |
14 |
|
T56 |
1 |
| true |
429 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9318 |
1 |
|
T4 |
211 |
|
T6 |
23 |
|
T15 |
1 |
| others[1] |
807 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
17 |
| others[2] |
813 |
1 |
|
T6 |
24 |
|
T56 |
1 |
|
T27 |
17 |
| others[3] |
1401 |
1 |
|
T5 |
1 |
|
T6 |
29 |
|
T56 |
1 |
| false |
382 |
1 |
|
T6 |
8 |
|
T36 |
1 |
|
T27 |
8 |
| true |
447 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2268 |
1 |
|
T1 |
1 |
|
T4 |
38 |
|
T5 |
1 |
| others[1] |
2227 |
1 |
|
T4 |
48 |
|
T6 |
14 |
|
T18 |
1 |
| others[2] |
2259 |
1 |
|
T2 |
1 |
|
T4 |
40 |
|
T6 |
10 |
| others[3] |
3761 |
1 |
|
T4 |
62 |
|
T6 |
16 |
|
T15 |
1 |
| false |
1178 |
1 |
|
T4 |
23 |
|
T6 |
4 |
|
T16 |
1 |
| true |
1475 |
1 |
|
T14 |
1 |
|
T6 |
46 |
|
T38 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8758 |
1 |
|
T4 |
211 |
|
T6 |
11 |
|
T18 |
1 |
| others[1] |
267 |
1 |
|
T6 |
10 |
|
T17 |
1 |
|
T27 |
12 |
| others[2] |
278 |
1 |
|
T6 |
9 |
|
T27 |
12 |
|
T21 |
1 |
| others[3] |
472 |
1 |
|
T14 |
1 |
|
T6 |
19 |
|
T15 |
1 |
| false |
128 |
1 |
|
T6 |
2 |
|
T27 |
2 |
|
T60 |
8 |
| true |
3265 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |