Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8984 |
1 |
|
T4 |
211 |
|
T6 |
9 |
|
T32 |
1 |
| others[1] |
447 |
1 |
|
T5 |
1 |
|
T6 |
14 |
|
T38 |
1 |
| others[2] |
499 |
1 |
|
T6 |
6 |
|
T36 |
1 |
|
T27 |
12 |
| others[3] |
789 |
1 |
|
T6 |
12 |
|
T56 |
1 |
|
T52 |
1 |
| false |
217 |
1 |
|
T6 |
3 |
|
T16 |
1 |
|
T56 |
1 |
| true |
2232 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8732 |
1 |
|
T4 |
211 |
|
T6 |
9 |
|
T42 |
52 |
| others[1] |
236 |
1 |
|
T6 |
6 |
|
T27 |
11 |
|
T60 |
4 |
| others[2] |
258 |
1 |
|
T6 |
10 |
|
T15 |
1 |
|
T27 |
4 |
| others[3] |
443 |
1 |
|
T6 |
21 |
|
T38 |
1 |
|
T56 |
1 |
| false |
131 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
5 |
| true |
3368 |
1 |
|
T14 |
1 |
|
T5 |
1 |
|
T6 |
50 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8753 |
1 |
|
T4 |
211 |
|
T6 |
5 |
|
T17 |
1 |
| others[1] |
277 |
1 |
|
T6 |
6 |
|
T27 |
18 |
|
T60 |
8 |
| others[2] |
279 |
1 |
|
T5 |
1 |
|
T6 |
16 |
|
T16 |
1 |
| others[3] |
362 |
1 |
|
T6 |
17 |
|
T91 |
1 |
|
T27 |
10 |
| false |
132 |
1 |
|
T6 |
4 |
|
T27 |
5 |
|
T60 |
4 |
| true |
3365 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9322 |
1 |
|
T2 |
1 |
|
T4 |
211 |
|
T6 |
20 |
| others[1] |
800 |
1 |
|
T6 |
21 |
|
T56 |
1 |
|
T53 |
1 |
| others[2] |
826 |
1 |
|
T6 |
23 |
|
T91 |
1 |
|
T27 |
21 |
| others[3] |
1369 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
30 |
| false |
411 |
1 |
|
T6 |
7 |
|
T27 |
11 |
|
T21 |
1 |
| true |
440 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9290 |
1 |
|
T2 |
1 |
|
T4 |
211 |
|
T5 |
1 |
| others[1] |
796 |
1 |
|
T6 |
12 |
|
T91 |
1 |
|
T27 |
18 |
| others[2] |
864 |
1 |
|
T1 |
1 |
|
T6 |
21 |
|
T38 |
1 |
| others[3] |
1350 |
1 |
|
T6 |
43 |
|
T15 |
1 |
|
T53 |
1 |
| false |
424 |
1 |
|
T6 |
8 |
|
T27 |
8 |
|
T60 |
11 |
| true |
444 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2264 |
1 |
|
T4 |
33 |
|
T6 |
14 |
|
T42 |
8 |
| others[1] |
2219 |
1 |
|
T4 |
40 |
|
T6 |
3 |
|
T17 |
1 |
| others[2] |
2306 |
1 |
|
T2 |
1 |
|
T4 |
43 |
|
T6 |
16 |
| others[3] |
3771 |
1 |
|
T4 |
79 |
|
T5 |
1 |
|
T6 |
19 |
| false |
1141 |
1 |
|
T1 |
1 |
|
T4 |
16 |
|
T6 |
6 |
| true |
1467 |
1 |
|
T14 |
1 |
|
T6 |
43 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8769 |
1 |
|
T4 |
211 |
|
T6 |
9 |
|
T42 |
52 |
| others[1] |
257 |
1 |
|
T6 |
6 |
|
T27 |
8 |
|
T60 |
10 |
| others[2] |
260 |
1 |
|
T6 |
9 |
|
T27 |
8 |
|
T21 |
1 |
| others[3] |
438 |
1 |
|
T6 |
15 |
|
T15 |
1 |
|
T16 |
1 |
| false |
142 |
1 |
|
T1 |
1 |
|
T6 |
4 |
|
T27 |
5 |
| true |
3302 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8987 |
1 |
|
T4 |
211 |
|
T6 |
11 |
|
T42 |
52 |
| others[1] |
472 |
1 |
|
T6 |
14 |
|
T27 |
5 |
|
T55 |
1 |
| others[2] |
439 |
1 |
|
T2 |
1 |
|
T6 |
10 |
|
T15 |
1 |
| others[3] |
832 |
1 |
|
T14 |
1 |
|
T6 |
20 |
|
T32 |
1 |
| false |
252 |
1 |
|
T6 |
2 |
|
T54 |
1 |
|
T27 |
8 |
| true |
2186 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
44 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8766 |
1 |
|
T4 |
211 |
|
T6 |
10 |
|
T42 |
52 |
| others[1] |
239 |
1 |
|
T6 |
11 |
|
T17 |
1 |
|
T32 |
1 |
| others[2] |
241 |
1 |
|
T6 |
10 |
|
T16 |
1 |
|
T27 |
8 |
| others[3] |
402 |
1 |
|
T1 |
1 |
|
T6 |
20 |
|
T15 |
1 |
| false |
152 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T27 |
8 |
| true |
3368 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T6 |
45 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8759 |
1 |
|
T4 |
211 |
|
T5 |
1 |
|
T6 |
10 |
| others[1] |
288 |
1 |
|
T6 |
8 |
|
T17 |
1 |
|
T53 |
1 |
| others[2] |
260 |
1 |
|
T6 |
10 |
|
T27 |
8 |
|
T60 |
11 |
| others[3] |
401 |
1 |
|
T6 |
14 |
|
T18 |
1 |
|
T32 |
1 |
| false |
109 |
1 |
|
T6 |
5 |
|
T36 |
1 |
|
T27 |
4 |
| true |
3351 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9305 |
1 |
|
T4 |
211 |
|
T5 |
1 |
|
T6 |
20 |
| others[1] |
784 |
1 |
|
T2 |
1 |
|
T6 |
19 |
|
T27 |
15 |
| others[2] |
860 |
1 |
|
T6 |
22 |
|
T18 |
1 |
|
T56 |
1 |
| others[3] |
1371 |
1 |
|
T1 |
1 |
|
T6 |
33 |
|
T15 |
1 |
| false |
408 |
1 |
|
T6 |
7 |
|
T27 |
7 |
|
T60 |
11 |
| true |
440 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9337 |
1 |
|
T4 |
211 |
|
T6 |
22 |
|
T42 |
52 |
| others[1] |
832 |
1 |
|
T1 |
1 |
|
T6 |
21 |
|
T15 |
1 |
| others[2] |
827 |
1 |
|
T6 |
20 |
|
T56 |
1 |
|
T27 |
21 |
| others[3] |
1306 |
1 |
|
T5 |
1 |
|
T6 |
27 |
|
T18 |
1 |
| false |
421 |
1 |
|
T2 |
1 |
|
T6 |
11 |
|
T53 |
1 |
| true |
445 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2291 |
1 |
|
T4 |
48 |
|
T6 |
11 |
|
T15 |
1 |
| others[1] |
2212 |
1 |
|
T2 |
1 |
|
T4 |
39 |
|
T6 |
14 |
| others[2] |
2245 |
1 |
|
T4 |
33 |
|
T6 |
5 |
|
T18 |
1 |
| others[3] |
3775 |
1 |
|
T4 |
70 |
|
T5 |
1 |
|
T6 |
20 |
| false |
1138 |
1 |
|
T1 |
1 |
|
T4 |
21 |
|
T6 |
5 |
| true |
1507 |
1 |
|
T14 |
1 |
|
T6 |
46 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8780 |
1 |
|
T4 |
211 |
|
T14 |
1 |
|
T6 |
12 |
| others[1] |
274 |
1 |
|
T6 |
13 |
|
T56 |
1 |
|
T27 |
11 |
| others[2] |
268 |
1 |
|
T6 |
2 |
|
T27 |
9 |
|
T21 |
1 |
| others[3] |
470 |
1 |
|
T2 |
1 |
|
T6 |
20 |
|
T91 |
1 |
| false |
127 |
1 |
|
T6 |
6 |
|
T18 |
1 |
|
T27 |
2 |
| true |
3249 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8974 |
1 |
|
T4 |
211 |
|
T6 |
11 |
|
T42 |
52 |
| others[1] |
481 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T17 |
1 |
| others[2] |
463 |
1 |
|
T6 |
6 |
|
T10 |
1 |
|
T91 |
1 |
| others[3] |
755 |
1 |
|
T14 |
1 |
|
T6 |
19 |
|
T56 |
2 |
| false |
258 |
1 |
|
T6 |
5 |
|
T54 |
1 |
|
T27 |
1 |
| true |
2237 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T6 |
55 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8764 |
1 |
|
T4 |
211 |
|
T6 |
8 |
|
T38 |
1 |
| others[1] |
254 |
1 |
|
T6 |
11 |
|
T56 |
1 |
|
T27 |
12 |
| others[2] |
240 |
1 |
|
T6 |
9 |
|
T17 |
1 |
|
T53 |
1 |
| others[3] |
450 |
1 |
|
T5 |
1 |
|
T6 |
11 |
|
T32 |
1 |
| false |
130 |
1 |
|
T6 |
6 |
|
T27 |
4 |
|
T60 |
6 |
| true |
3330 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8742 |
1 |
|
T4 |
211 |
|
T6 |
10 |
|
T16 |
1 |
| others[1] |
297 |
1 |
|
T6 |
8 |
|
T32 |
1 |
|
T53 |
1 |
| others[2] |
236 |
1 |
|
T6 |
8 |
|
T18 |
1 |
|
T27 |
9 |
| others[3] |
424 |
1 |
|
T5 |
1 |
|
T6 |
17 |
|
T27 |
19 |
| false |
146 |
1 |
|
T1 |
1 |
|
T6 |
4 |
|
T17 |
1 |
| true |
3323 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T6 |
54 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9286 |
1 |
|
T2 |
1 |
|
T4 |
211 |
|
T6 |
14 |
| others[1] |
810 |
1 |
|
T6 |
23 |
|
T91 |
1 |
|
T27 |
18 |
| others[2] |
811 |
1 |
|
T6 |
16 |
|
T27 |
22 |
|
T60 |
24 |
| others[3] |
1384 |
1 |
|
T1 |
1 |
|
T6 |
40 |
|
T27 |
41 |
| false |
444 |
1 |
|
T5 |
1 |
|
T6 |
8 |
|
T53 |
1 |
| true |
433 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9331 |
1 |
|
T4 |
211 |
|
T5 |
1 |
|
T6 |
22 |
| others[1] |
790 |
1 |
|
T2 |
1 |
|
T6 |
14 |
|
T56 |
1 |
| others[2] |
815 |
1 |
|
T6 |
22 |
|
T15 |
1 |
|
T18 |
1 |
| others[3] |
1348 |
1 |
|
T1 |
1 |
|
T6 |
34 |
|
T38 |
1 |
| false |
430 |
1 |
|
T6 |
9 |
|
T27 |
9 |
|
T60 |
13 |
| true |
454 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2302 |
1 |
|
T4 |
34 |
|
T6 |
9 |
|
T42 |
9 |
| others[1] |
2148 |
1 |
|
T2 |
1 |
|
T4 |
39 |
|
T6 |
7 |
| others[2] |
2222 |
1 |
|
T1 |
1 |
|
T4 |
34 |
|
T6 |
17 |
| others[3] |
3819 |
1 |
|
T4 |
83 |
|
T5 |
1 |
|
T6 |
16 |
| false |
1192 |
1 |
|
T4 |
21 |
|
T6 |
7 |
|
T42 |
6 |
| true |
1485 |
1 |
|
T14 |
1 |
|
T6 |
45 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8772 |
1 |
|
T4 |
211 |
|
T5 |
1 |
|
T6 |
11 |
| others[1] |
272 |
1 |
|
T6 |
10 |
|
T38 |
1 |
|
T27 |
10 |
| others[2] |
278 |
1 |
|
T6 |
14 |
|
T16 |
1 |
|
T91 |
1 |
| others[3] |
439 |
1 |
|
T2 |
1 |
|
T6 |
15 |
|
T18 |
1 |
| false |
145 |
1 |
|
T6 |
4 |
|
T15 |
1 |
|
T27 |
10 |
| true |
3262 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T6 |
47 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8963 |
1 |
|
T4 |
211 |
|
T6 |
7 |
|
T16 |
1 |
| others[1] |
483 |
1 |
|
T5 |
1 |
|
T6 |
5 |
|
T56 |
1 |
| others[2] |
442 |
1 |
|
T6 |
11 |
|
T17 |
1 |
|
T56 |
1 |
| others[3] |
827 |
1 |
|
T6 |
18 |
|
T15 |
1 |
|
T27 |
18 |
| false |
242 |
1 |
|
T6 |
5 |
|
T32 |
1 |
|
T36 |
1 |
| true |
2211 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8732 |
1 |
|
T4 |
211 |
|
T6 |
9 |
|
T42 |
52 |
| others[1] |
251 |
1 |
|
T6 |
15 |
|
T16 |
1 |
|
T18 |
1 |
| others[2] |
242 |
1 |
|
T5 |
1 |
|
T6 |
9 |
|
T56 |
1 |
| others[3] |
470 |
1 |
|
T6 |
17 |
|
T17 |
1 |
|
T32 |
1 |
| false |
133 |
1 |
|
T1 |
1 |
|
T6 |
5 |
|
T56 |
1 |
| true |
3340 |
1 |
|
T2 |
1 |
|
T14 |
1 |
|
T6 |
46 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8771 |
1 |
|
T4 |
211 |
|
T6 |
8 |
|
T42 |
52 |
| others[1] |
242 |
1 |
|
T6 |
8 |
|
T16 |
1 |
|
T53 |
1 |
| others[2] |
266 |
1 |
|
T6 |
18 |
|
T18 |
1 |
|
T56 |
1 |
| others[3] |
394 |
1 |
|
T2 |
1 |
|
T6 |
12 |
|
T38 |
1 |
| false |
144 |
1 |
|
T6 |
5 |
|
T36 |
1 |
|
T27 |
4 |
| true |
3351 |
1 |
|
T1 |
1 |
|
T14 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9316 |
1 |
|
T2 |
1 |
|
T4 |
211 |
|
T6 |
17 |
| others[1] |
846 |
1 |
|
T6 |
20 |
|
T71 |
1 |
|
T36 |
1 |
| others[2] |
795 |
1 |
|
T6 |
21 |
|
T27 |
25 |
|
T60 |
15 |
| others[3] |
1387 |
1 |
|
T6 |
35 |
|
T18 |
1 |
|
T91 |
1 |
| false |
414 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T6 |
8 |
| true |
410 |
1 |
|
T14 |
1 |
|
T16 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |